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Mobile SoC Verification. Full Chip Verification of Hardware, Software, and Peripherals Chen, ZaiMan Emulation Business Development Manager, Mentor. Agenda. Trends and challenges in system-on-chip verification Mentor’s solution for Multi-core SOC chip verification Summary.

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mobile soc verification

Mobile SoCVerification

Full Chip Verification of Hardware, Software, and Peripherals

Chen, ZaiMan

Emulation Business Development Manager, Mentor

agenda
Agenda

Trends and challenges in system-on-chip verification

Mentor’s solution for Multi-core SOC chip verification

Summary

Total SOC Verification TDF 2012

78 of all designs have embedded processors
78% of all Designs Have Embedded Processors

   2004 – mean # embedded processor1.06

  •    2007 – mean # embedded processor 1.46
  •    2010 – mean # embedded processor 2.14

Responses

Wilson Research Group

Wilson Research Group and Mentor Graphics

2010 Functional Verification Study, Used with permission

Total SOC Verification TDF 2012

arm embedded processors dominate soc
ARM Embedded Processors Dominate SoC

35% increase in ARM embedded processor core adoption!

Responses

Wilson Research Group

Wilson Research Group and Mentor Graphics

2010 Functional Verification Study, Used with permission

Total SOC Verification TDF 2012

what s changed in design and verification trends it s the software stupid gary smith
What’s changed in design and verification?Trends: It’s the software—stupid! -Gary Smith

Software is fastest growing component of SoC development cost

All this software requires a lot of verification!

Source: 2007 ITRS Roadmap

Total SOC Verification TDF 2012

flatline
Flatline

What do you do when your processor goes into “flatline” or just stops working?

RAK Sept 2008

agenda1
Agenda

Trends and challenges in system-on-chip verification

Mentor’s solution for Multi-core SOC chip verification

Summary

Total SOC Verification TDF 2012

driving the virtual target environment
Driving the Virtual Target Environment

Simulation Acceleration

OVM/UVM

SystemVerilog

SystemC

Transactors (xMVCs)

SW Debug

VStream

Codelink

Co-Model Channel

Debug Port Transactor (JTAG)

Testbench Xpress

Virtual Peripherals

....

USB

PCIe

Video

Ethernet

Design IP and virtual iSolve

Physical Peripherals (ICE)

....

Physical I/O

USB

PCIe

Video

JTAG

iSolve

Total SOC Verification TDF 2012

veloce family
Veloce Family

Veloce Trio

Veloce Solo

Veloce Quattro

Veloce Grande

Veloce Maximus

Single Silicon Technology, Common Logic Board, Compile S/W, Debug/UI

Total SOC Verification TDF 2012

emulate a mobile chip on veloce
Emulate a Mobile chip on Veloce
  • Digital IQ interface
    • EX-IQ box: Adapting the R&S I/Q-interface for Emulation (iSolve DigIQ)
    • Reduced system clock rate  Slow IQ to adapt from full speeds to SoC Emulation

Protocol Test

R&S CMW500

UE BaseBand chip

R&S EX-IQ

Stimulus Gen

iSolve DigIQ I/F

R&S SMU200

R&S Ex-IQ Box

Analyze

R&S FSV/FSU

codelink architecture velcoe
CodelinkArchitecture - Velcoe

Replay

Database

Waveform View

SW Debugger

Codelink

Replay

Server

Standard GDB

RSP interface

economical support for many sw engineers
Economical Support for Many SW Engineers

JTAG online debug

Codelink offline SW debug

Codelink logfiles

Batch runs

JTAG probe

  • 4 hour session typical for online SW debug
  • Digital camera batch run was 20 minutes
  • Run 12 batch jobs in 4 hours

Support 10 times more SW engineers

Non-intrusive multi-core debug

Synchronized SW and HW views

10 times faster than JTAG

Total SOC Verification TDF 2012

functional verification trends emulation used for software development and integration
Functional Verification Trends- Emulation used for Software Development and Integration

Traditional

Verification Flow

HW Development

Fab

Integration

SW Development

Time-to-Market Reduced

  • Reduce time-to-market
  • Start software earlier
  • Verify hardware with software
  • Perform hardware/software trade-off analysis
  • Correct functional, architectural and performance issues in hardware before tape-out rather than in software later

Hardware Assisted

Verification Flow

HW Development

Fab

Integration

SW Development

Large Time-to-Market potential

summary
Summary
  • HW/SW co-verification becomes more challenging and important
  • Veloce + Tester can help you to setup system level verification solution
  • Veloce + Codelink can provide unique methodology in SW/HW co-verification

DAC 2012