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Implementation of ECC in Combo6X Card

This study presents the implementation of Elliptic Curve Cryptography (ECC) in Combo6X Card, focusing on cryptographic processor design, arithmetic units, controller, and I/O unit. The ECC offers efficient and secure public key cryptography. The interchangeable arithmetic units enhance flexibility, while the programmable controller allows for future modifications and firmware updates. Successful integration and scalability of ECC in Combo6X framework are highlighted.

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Implementation of ECC in Combo6X Card

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  1. Implementation of ECC in Combo6X Card Tomáš Davidovič, Martin Havlan, Martin Novotný, Pavel Bezpalec CTU FEE in Prague

  2. Outline • Introduction • Cryptographic Processor • Arithmetic units • Controller and I/O • Conclusions

  3. Elliptic Curve Cryptography (ECC) • ECC – belongs to class of asymmetric ciphers (public key cryptography) • ECC gradually replaces RSA algorithm (smart cards, ID systems, …) • ECC needs simpler hardware for the same strength • e.g.: ECC: 160 bit keys  RSA:1024 bit keys

  4. Cryptographic Processor • Should evaluate the scalar point multiple Q = kP = P + P + … + P (k-times) where: Q, P – points on elliptic curve k – integer • Point coordinates are elements of binary finite field GF(2m) • Point coordinates can be represented in both polynomial and normal basis • Interchangeable arithmetic units (polynomial basis AU  normal basis AU)

  5. Cryptographic Processor • Polynomial Basis AU • Normal Basis AU Or • Both AU switched on-the-fly Interchangeable Arithmetic Unit

  6. Polynomial AU – Inverter • Both multiplication and inversion • One set of registers for both • Multiplication – digits of arbitrary length • Inversion – speed up still researched • Several versions are tested • Two sets of registers • cost more in the means of DFF, but require less logic. • Worse for ASIC, but possibly better for FPGA

  7. AU – Squarer • Purely combination circuit • Logic depth max 3 XOR gates for 162 bits • Structure dependant on • Key length • Reducing polynomial for the length • Previously: Netlist generated by C program

  8. AU – current Squarer • State-of-the-art synthesis tools allow more • Behavioral description synthesized correctly • Only need: • List of polynomials • Required length • Transparent code • No need of external tools • Possibly better synthesis options

  9. I/O unit • Arbitrary width of input • Arbitrary frequency of input • Full bound handshake • Two types of access possible • Serial • Always assumes read/write of adequate length • Shift registers • Addressed • Requires more complicated control from sender • Allows random access to the polynomials

  10. Controller • Programmable: • Program in ROM for more effective synthesis • Reprogrammable for further firmware modifications • Custom designed micro-ASM • Java compiler • Generates both ROM and RAM versions of program

  11. Future work • Perform evaluation in hardware • Combo6X FPGA • ASIC • Incorporate into Combo6X framework • Devise protocol using ECC authentication

  12. Conclusions • Bugs fixed – polynomial unit redesigned • Design passes all simulations • Both Polynomial and Normal basis AU are scalable • Design highly modular and programmable

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