1 / 12

Shailesh Radhakrishnan, Mingzhen Wang and Chien-In Henry Chen.

A Low-Power 4-b 2.5 Gsample/s Pipelined Flash Analog-to-Digital Converter Using Differential Comparator and DCVSPG Encoder. Shailesh Radhakrishnan, Mingzhen Wang and Chien-In Henry Chen. Department of Electrical Engineering Wright State University Dayton, USA, May,2005. 班級 ：積體碩一

ovid
Download Presentation

Shailesh Radhakrishnan, Mingzhen Wang and Chien-In Henry Chen.

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. A Low-Power 4-b 2.5 Gsample/s Pipelined Flash Analog-to-Digital Converter Using Differential Comparator and DCVSPG Encoder Shailesh Radhakrishnan, Mingzhen Wang and Chien-In Henry Chen. Department of Electrical Engineering Wright State University Dayton, USA, May,2005. 班級 ：積體碩一 姓名 ：黃順和 學號 ：95662009

  2. outline • 1. Introduction • 2. Pipelined Flash ADC • 3. Track-and-Hold Circuit • 4. Differential Comparator • 5. DCVSPG Encoder • 6. Experimental Results • 7. Conclusions • 8. References

  3. Introduction • Dual-array T/H achieves higher data throughput. The proposed ADC uses current mode, dual-array T/H. • Differential comparator has less susceptible to noise than TIQ comparator. Power consumption of the differential comparator is much less as compared to the TIQ comparator. • This paper presents a DCVSPG (differential cascode voltage switch with pass-gate) encoder which directly converts the thermometer code to binary code in one step.

  4. Pipelined Flash ADC

  5. Track-and-Hold Circuit

  6. Differential Comparator

  7. DCVSPG Encoder

  8. Experimental Results • The 4-bit flash ADC is designed and simulated in 130 nanometer CMOS. • Both INL and DNL as shown in the table are less than 0.3 LSB. The average power consumption is 23.78 mW. The simulation of the ADC with 250 MHz input signal. • The power consumption of the DCVSPG encoder is 88 % less than the conventional ROM encoder.

  9. ENCODER PERFORMANCE SUMMARY

  10. PERFORMANCE OF 4-BIT ADC

  11. Conclusions • The pipelined architecture achieves high data throughput and high speed by incorporating pipelined clocked track-and-hold and clocked DCVSPG encoder. • The pipelined CMOS ADC offers a data conversion rate of 2.5 GSPS while maintaining low power consumption. • The DCVSPG encoder overcomes the speed limitation of the ROM encoder which has been a bottleneck of high-speed ADCs.

  12. References • [1] F. Lai and W. Hwang, “Design and implementaion of differential cascode voltage switch with pass-gate (DCVSPG) logic for highperformance digital systems,” IEEE Journal of Solid-State Circuits, vol. 32, April 1997. • [2] J. Yoo, K. Choi, and J. Ghaznavi, “Quantum voltage comparator for 0.07 μm flash A/D converters,” Proceedings of the IEEE Computer Society Annual Symposium on VLSI, pp. 20-21, Feb. 2003. • [3] X. Jiang, Z. Wang and M.F. Chang, “A 2GS/s 6-b ADC in 0.18 μm CMOS,” IEEE International Solid-State Circuits Conference, vol. 1, pp. 9-13, Feb. 2003

More Related