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High Speed Memory Debug Techniques. presented by: Jennie Grosslight Project Development Manager Memory Solutions. FuturePlus ® Systems Corporation. Basic Strategy: Eliminate unlikely causes thru quick checks and automated tools so you can… Go deep on most likely causes with thorough checks.

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High speed memory debug techniques l.jpg

High Speed Memory Debug Techniques

presented by:Jennie GrosslightProject Development ManagerMemory Solutions

FuturePlus® Systems Corporation


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Basic Strategy:

Eliminate unlikely causes thru quick checks and automated tools so you can…

Go deep on most likely causes with thorough checks

High Speed Memory Debug Techniques


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Marginal timing relationships

Protocol violation

Clock integrity issues

SI failures

Other possibilities

Incorrect BIOS setting for On Die Termination (ODT)

Invalid Cas latency

Errors from other buses

Typical Causes of Memory Failures


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High Speed Memory Debug Techniques

  • Determine if the failure is repeatable.

  • Connect a logic analyzer to the memory bus with a probe or interposer to gain rapid insight  

  • Run SW tests on LA traces  

  • Parametric measurements

Applicable to any SDRAM, Embedded or Standard Slots


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Root cause of the problem can come from a sub-system or applications that are not directly connected to memory.

LAN access, power sequences of subsystems, entering and exiting sleep modes, and power cycles. Cross talk and conflicting resources from a variety of sub-systems, modes, and cycles.

Isolation of a problem during a specific test or set of conditions  

Review error logs and identifying what software was running at the time of the failure.

Environmental variants - What was the room temperature when the system failed? Check the airflow to system.

Determine if failure is repeatable


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Hardware - Is the power to the system within specifications? Has a system of this same design ever passed validation tests?

Do other systems fail or is this failure unit specific?

What are the revisions on the board, DIMM, processor, or other components of the failed system?

How does the failed system differ from working systems?

Have there been recent component changes in manufacturing?

If conditions are repeatable, run your tests under those conditions, if not chose a robust memory test and vary the test conditions, such as temperature and power supply limits, in a methodical manner.

Determine if failure is repeatable


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High Speed Memory Debug Techniques specifications? Has a system of this same design ever passed validation tests?

  • Determine if the failure is repeatable.

  • Connect a logic analyzer to the memory bus with a probe or interposer to gain rapid insight

    • Timing Zoom

    • Eye finder and Eye Scan

    • State listing/waveforms

    • Markers

    • Filters

  • Run SW tests on LA traces  

  • Parametric measurements

Applicable to any SDRAM, Embedded or Standard Slots


Timing relationships l.jpg
Timing Relationships specifications? Has a system of this same design ever passed validation tests?

  • Key Points:

    • LA provides rapid insight of timing relationships of entire bus.

    • 64k of high resolution timing adjustable about trigger

    • Markers for quick measurements

      • Clock frequency

      • Data valid windows

      • CAS latency

64k deep 250ps resolution trace


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Eye Finder – Insight-at-a-glance specifications? Has a system of this same design ever passed validation tests?

Clock Signal Integrity

Time=0=clock edge

  • In this example, lower screen reveals Clock noise. Apparent by wider transition area at Time=0=clock edge.

  • Additional information

    • Setup /hold of address and control lines

    • Relative skew of address/control signals

Clean clock

Dirty clock


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Eye Scan – In depth insight specifications? Has a system of this same design ever passed validation tests?

  • 10ps / 5mV resolution eye diagrams

  • Rapid Detection

    • signals with parts per million errors

    • Skew

  • Recognition of Parts per Million error allows in depth investigation of signals with errors as opposed to investigating all signals


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State trace list with protocol decode allows detailed protocol check

Global markers placed in State or Waveform window track to all LA windows

View Specific Violations


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Markers and Measurements protocol check


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Examples of Failures protocol check

Protocol Error

Patterns left to right:

  • B0 Activate (pink)

  • B0 Writes (red)

  • B1 Activate Missing (turquoise)

  • B1 Read (light blue)

  • Using Colorized filter for pattern recognition. Patterns possible include:

    • RAS / CAS delay

    • CAS latency

    • Precharge interval

    • Overview of memory access

    • Page access pattern


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High Speed Memory Debug Techniques protocol check

  • Determine if the failure is repeatable.  

  • Connect a logic analyzer to the memory bus with a probe or interposer to gain rapid insight

  • Run SW tests on LA traces  

  • Parametric measurements

Applicable to any SDRAM, Embedded or Standard Slots




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High Speed Memory Debug Techniques protocol check

  • Determine if the failure is repeatable.  

  • Connect a logic analyzer to the memory bus with a probe or interposer to gain rapid insight  

  • Run SW tests on LA traces  

  • Parametric measurements

Applicable to any SDRAM, Embedded or Standard Slots


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Comprehensive Data Analysis protocol check

Complete Jitter Analysis

RJ/DJ (ISI,DCD, Periodic jitter) separation

Jitter histograms

Spectral analysis

Traceable to individual bits

Bathtub BER analysis

Masks

Real Time Eye

Eye unfolding identifies failure pattern

FBD Fixture control and compliance test suite integration


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Summary: protocol check

Eliminate unlikely causes thru quick checks and automated tools so you can…

Go deep on most likely causes with thorough checks

High Speed Memory Debug Techniques

FuturePlus® Systems Corporation