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Computer Arithmetic Chapter 3. Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu. What Goes on Inside ALU?. Machine instr.: add $t1, $s1, $s2

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Computer arithmetic chapter 3 l.jpg

Computer ArithmeticChapter 3

Vishwani D. Agrawal

James J. Danaher Professor

Department of Electrical and Computer Engineering

Auburn University

http://www.eng.auburn.edu/~vagrawal

vagrawal@eng.auburn.edu

ELEC 5200-001/6200-001 Lecture 7


What goes on inside alu l.jpg
What Goes on Inside ALU?

  • Machine instr.: add $t1, $s1, $s2

  • What it means to computer:

    000000 10001 10010 01000 00000 100000

Arithmetic Logic Unit

(ALU)

Control unit

Flags

Registers

Registers

ELEC 5200-001/6200-001 Lecture 7


Basic idea l.jpg
Basic Idea

  • Hardware can only deal with binary digits, 0 and 1.

  • Must represent all numbers, integers or floating point, positive or negative, by binary digits, called bits.

  • Devise electronic circuits to perform arithmetic operations, add, subtract, multiply and divide, on binary numbers.

ELEC 5200-001/6200-001 Lecture 7


Positive integers l.jpg
Positive Integers

  • Decimal system: made of 10 digits, {0,1,2, . . . , 9}

    41 = 4×10 + 1

    255 = 2×102 + 5×101 + 5×100

  • Binary system: made of two digits, {0,1}

    00101001 = 0×27 + 0×26 + 1×25 + 0×24 +1×23

    +0×22 + 0×21 + 1×20

    =32 + 8 +1 = 41

    11111111 = 255, largest number with 8 binary digits

    28-1

ELEC 5200-001/6200-001 Lecture 7


Base or radix l.jpg
Base or Radix

  • For decimal system, 10 is called the base or radix.

  • Decimal 41 is also written as 4110 or 41ten

  • Base (radix) for binary system is 2.

  • Thus, 41ten = 1010012 or 101001two

  • Also, 111ten = 1101111two

    and 111two = 7ten

ELEC 5200-001/6200-001 Lecture 7


Signed integers how not to do l.jpg
Signed Integers – How not to Do

  • Use fixed length binary representation

  • Use left-most bit (called most significant bit or MSB) for sign

    • 0 for positive

    • 1 for negative

  • Example: +18ten = 00010010two

    - 18ten = 10010010two

ELEC 5200-001/6200-001 Lecture 7


Why not signed integers l.jpg
Why Not Signed-Integers

  • Sign and magnitude bits should be differently treated in arithmetic operations.

  • Addition and subtraction require different logic circuits.

  • Overflow is difficult to detect.

  • “Zero” has two representations:

    • +0ten = 00000000two

    • - 0ten = 10000000two

  • Signed-integers are not used in modern computers.

ELEC 5200-001/6200-001 Lecture 7


Signed integers other ways l.jpg
Signed Integers – Other Ways

  • Use fixed-length representation, but no sign bit

    • One’s complement: To form a negative number, complement each bit in the positive magnitude.

    • Two’s complement: To form a negative number, start with positive magnitude, subtract one, and then complement each bit, or

      first complement each bit in the positive magnitude, and then add one.

  • Two’s complement is the most preferred representation.

ELEC 5200-001/6200-001 Lecture 7


Three representations l.jpg
Three Representations

Sign-magnitude

000 = +0

001 = +1

010 = +2

011 = +3

100 = - 0

101 = - 1

110 = - 2

111 = - 3

One’s complement

000 = +0

001 = +1

010 = +2

011 = +3

100 = - 3

101 = - 2

110 = - 1

111 = - 0

Two’s complement

000 = +0

001 = +1

010 = +2

011 = +3

100 = - 4

101 = - 3

110 = - 2

111 = - 1

(Preferred)

ELEC 5200-001/6200-001 Lecture 7


Two s complement numbers l.jpg

000

001

0

111

1

-1

2

010

110

-2

-3

3

011

-4

101

100

Two’s Complement Numbers

ELEC 5200-001/6200-001 Lecture 7


Two s complement n bit numbers l.jpg
Two’s Complement n-bit Numbers

  • Range: -2n-1 through 2n-1- 1

  • Unique zero: 00000000 . . . . . 0

  • Negation rule: see slide 8.

  • Expansion of bit length: stretch the left-most bit all the way, e.g., 11111101 is still – 3.

  • Overflow rule: If two numbers with the same sign bit (both positive or both negative) are added, the overflow occurs if and only if the result has the opposite sign.

  • Subtraction rule: for A-B, add –B to A.

ELEC 5200-001/6200-001 Lecture 7


Converting two s compliment to decimal l.jpg
Converting Two’s Compliment to Decimal

n-1

an-1an-2 . . . a1a0 = -2n-1an-1 + Σ 2i ai

i=0

8-bit conversion box

-128 64 32 16 8 4 2 1

-128 64 32 16 8 4 2 1

1 1 1 1 1 1 0 1

Example

-128+64+32+16+8+4+1 = -128 + 125 = -3

ELEC 5200-001/6200-001 Lecture 7


Slide13 l.jpg
MIPS

  • MIPS architecture uses 32-bit numbers. What is the range of integers (positive and negative) that can be represented?

    Positive integers: 0 to 2,147,483,647

    Negative integers: -1 to -2,147,483,648

  • What are the binary representations of the extreme positive and negative integers?

    0111 1111 1111 1111 1111 1111 1111 1111 = 231-1 = 2,147,483,647

    1000 0000 0000 0000 0000 0000 0000 0000 = -231 = -2,147,483,648

  • What is the binary representation of zero?

    0000 0000 0000 0000 0000 0000 0000 0000

ELEC 5200-001/6200-001 Lecture 7


Addition l.jpg
Addition

  • Adding bits:

    • 0 + 0 = 0

    • 0 + 1 = 1

    • 1 + 0 = 1

    • 1 + 1 = (1)0

  • Adding integers:

carry

1 1 0

0 0 0 . . . . . . 0 1 1 1 two = 7ten

+ 0 0 0 . . . . . . 0 1 1 0 two = 6ten

= 0 0 0 . . . . . . 1 (1) 1 (1) 0 (0) 1 two = 13ten

ELEC 5200-001/6200-001 Lecture 7


Subtraction l.jpg
Subtraction

  • Direct subtraction

  • Two’s complement subtraction

0 0 0 . . . . . . 0 1 1 1 two = 7ten

- 0 0 0 . . . . . . 0 1 1 0 two = 6ten

= 0 0 0 . . . . . . 0 0 0 1two = 1ten

1 1 0

0 0 0 . . . . . . 0 1 1 1 two = 7ten

+ 1 1 1 . . . . . . 1 0 1 0 two = - 6ten

= 0 0 0 . . . . . . 0 (1) 0 (1) 0 (0)1 two = 1ten

ELEC 5200-001/6200-001 Lecture 7


Overflow an error l.jpg
Overflow: An Error

  • Examples: Addition of 3-bit integers (range -4 to +3)

    • -2-3 = -5 110 = -2

      + 101 = -3

      = 1011 = 3 (error)

    • 3+2 = 5 011 = 3

      010 = 2

      = 101 = -3 (error)

  • Overflow rule: If two numbers with the same sign bit (both positive or both negative) are added, the overflow occurs if and only if the result has the opposite sign.

000

111

0

001

1

-1

2

010

110

-2

3

-3

011

-4

101

100

ELEC 5200-001/6200-001 Lecture 7


Test 1 result l.jpg
Test 1 Result

Average = 19.9

Max = 23.5

Min = 14.5

Number of students

Score range

ELEC 5200-001/6200-001 Lecture 7


Design hardware bit by bit l.jpg

a

half_sum

XOR

b

carry_out

AND

Design Hardware Bit by Bit

  • Adding two bits:

    a b half_sum carry_out

    0 0 0 0

    0 1 1 0

    1 0 1 0

    1 1 0 1

  • Half-adder circuit

ELEC 5200-001/6200-001 Lecture 7


One bit full adder l.jpg
One-bit Full-Adder

  • One-bit full-adder truth table

    a b ci half_sum carry_out sum co

    0 0 0 0 0 0 0

    0 0 1 0 0 1 0

    0 1 0 1 0 1 0

    0 1 1 1 0 0 1

    1 0 0 1 0 1 0

    1 0 1 1 0 0 1

    1 1 0 0 1 0 1

    1 1 1 0 1 1 1

ELEC 5200-001/6200-001 Lecture 7


One bit full adder circuit l.jpg
One-bit Full-Adder Circuit

ci

FAi

XOR

sumi

ai

XOR

AND

bi

AND

OR

Ci+1

ELEC 5200-001/6200-001 Lecture 7


32 bit ripple carry adder l.jpg
32-bit Ripple-Carry Adder

c0

a0

b0

sum0

FA0

sum1

a1

b1

FA1

sum2

a2

b2

FA2

sum31

FA31

a31

b31

ELEC 5200-001/6200-001 Lecture 7


How fast is ripple carry adder l.jpg
How Fast is Ripple-Carry Adder?

  • Longest delay path (critical path) runs from cin to sum31.

  • Suppose delay of full-adder is 100ps.

  • Critical path delay = 3,200ps

  • Clock rate cannot be higher than 1012/3,200 = 312MHz.

  • Must use more efficient ways to handle carry.

ELEC 5200-001/6200-001 Lecture 7


Speeding up the adder l.jpg

a0-a15

16-bit

ripple

carry

adder

b0-b15

cin

Speeding Up the Adder

sum0-sum15

a16-a31

16-bit

ripple

carry

adder

0

b16-b31

0

sum16-sum31

Multiplexer

a16-a31

16-bit

ripple

carry

adder

1

b16-b31

This is known as

carry-select adder

1

ELEC 5200-001/6200-001 Lecture 7


Fast adders l.jpg
Fast Adders

  • In general, any output of a 32-bit adder can be evaluated as a logic expression in terms of all 65 inputs.

  • Levels of logic in the circuit can be reduced to log2N for N-bit adder. Ripple-carry has N levels.

  • More gates are needed, about log2N times that of ripple-carry design.

  • Fastest design is known as carry lookahead adder.

ELEC 5200-001/6200-001 Lecture 7


N bit adder design options l.jpg
N-bit Adder Design Options

Reference: J. L. Hennessy and D. A. Patterson, Computer Architecture:

A Quantitative Approach, Second Edition, San Francisco, California,

1990.

ELEC 5200-001/6200-001 Lecture 7


Mips instructions see p 175 l.jpg
MIPS Instructions (see p. 175)

  • Arithmetic: add, sub, addi, addu, subu, addiu, mfc0

  • Data transfer: lw, sw, lhu, sh, lbu, sb, lui

  • Logical: and, or, nor, andi, ori, sll, srl

  • Conditional branch: beq, bne, slt, slti, sltu, sltiu

  • Unconditional jump: j, jr, jal

ELEC 5200-001/6200-001 Lecture 7


Exception or interrupt l.jpg
Exception or Interrupt

  • If an overflow is detected while executing add, addi or sub, then the address of that instruction is placed in a register called exception program counter (EPC).

  • Instruction mfc0 can copy $epc to any other register, e.g., mfc0 $s1, $epc

  • Unsigned operations, addu, addiu and subu do not cause an exception or interrupt.

ELEC 5200-001/6200-001 Lecture 7


Multifunction alu l.jpg
Multifunction ALU

operation

c0

a0

b0

result0

ALU0

result1

a1

b1

ALU1

result2

operation

a2

b2

ALU2

ci

ai

bi

FAi

3

NOR

2

resulti

mux

OR

1

result31

ALU31

a31

b31

AND

0

ELEC 5200-001/6200-001 Lecture 7


Binary multiplication unsigned l.jpg
Binary Multiplication (Unsigned)

1 0 0 0 two = 8ten multiplicand

1 0 0 1 two = 9ten multiplier

____________

1 0 0 0

0 0 0 0 partial products

0 0 0 0

1 0 0 0

____________

1 0 0 1 0 0 0two = 72ten

ELEC 5200-001/6200-001 Lecture 7


Multiplication flowchart l.jpg
Multiplication Flowchart

Start

Initialize product register to 0

Partial product number, i = 1

LSB

of multiplier

?

Add multiplicand to

product and place result

in product register

1

0

Left shift multiplicand register 1 bit

Right shift multiplier register 1 bit

i = 32

i < 32

i = ?

Done

i = i + 1

ELEC 5200-001/6200-001 Lecture 7


Serial multiplication l.jpg
Serial Multiplication

shift left

shift right

Multiplicand

32-bit multiplier

64

LSB

32 times

64

Control

test

64-bit ALU

64

64-bit product register

write

3 operations per bit

ELEC 5200-001/6200-001 Lecture 7


Serial multiplication improved l.jpg
Serial Multiplication (Improved)

Multiplicand

2 operations per bit

32

32

Control

test

32-bit ALU

LSB

32 times

32

write

64-bit product register

shift right

00000 . . . 00000 32-bit multiplier

Initialized prod. Reg.

ELEC 5200-001/6200-001 Lecture 7


Example 0010 two 0011 two l.jpg
Example: 0010two× 0011two

ELEC 5200-001/6200-001 Lecture 7


Signed multiplication l.jpg
Signed Multiplication

  • Convert numbers into magnitudes.

  • Multiply the two magnitudes through 32 iterations.

  • Negate the result if the signs of the multiplicand and multiplier differed.

  • A better method: Booth Algorithm.

  • Time of serial multiplication: O(N) clock cycles for N-bit integers.

ELEC 5200-001/6200-001 Lecture 7


Booth multiplier algorithm l.jpg
Booth Multiplier Algorithm

  • A. D. Booth, “A Signed Binary Multiplication Technique,” Quarterly Journal of Mechanics and Applied Math., vol. 4, pt. 2, pp. 236-240, 1951.

  • Direct multiplication of positive and negative integers using two’s complement addition.

ELEC 5200-001/6200-001 Lecture 7


Booth algorithm basic idea l.jpg
Booth Algorithm: Basic Idea

  • Consider a multiplier, 00011110 (30)

    • We can write, 30 = 32 – 2, or

      00100000 (32) = 25

      +11111110 (-2) = -21

      00011110 30

  • Interpret multiplier (scan right to left), check bit-pairs:

    • kth bit is 1, (k-1)th bit is 0, multiplier contains -2k term

    • kth bit is 0, (k-1)th bit is 1, multiplier contains 2kterm

    • kth bit is 0, (k-1)th bit is 1, 2k is absent in multiplier

    • kth bit is 1, (k-1)th bit is 0, 2k is absent in multiplier

  • Product, M×30 = M×25 - M×21 M: multiplicand

  • Multiplication by 2k means a k-bit left shift

ELEC 5200-001/6200-001 Lecture 7


Booth algorithm example 1 l.jpg
Booth Algorithm: Example 1

  • 7 × 3 = 21

    0111 multiplicand = 7

    ×0011(0) multiplier = 3

    11111001 bit-pair 10, add -7 in two’s compl.

    bit-pair 11, do nothing

    000111 bit-pair 01, add 7

    bit-pair 00, do nothing

    00010101 21

ELEC 5200-001/6200-001 Lecture 7


Booth algorithm example 2 l.jpg
Booth Algorithm: Example 2

  • 7 × (-3) = -21

    0111 multiplicand = 7

    ×1101(0) multiplier = -3

    11111001 bit-pair 10, add -7 in two’s compl.

    0000111 bit-pair 01, add 7

    111001 bit-pair 10, add -7 in two’s compl.

    bit-pair 11, do nothing

    11101011 -21

ELEC 5200-001/6200-001 Lecture 7


Booth algorithm example 3 l.jpg
Booth Algorithm: Example 3

  • -7 × 3 = -21

    1001 multiplicand = -7 in two’s com.

    ×0011(0) multiplier = 3

    00000111 bit-pair 10, add 7

    bit-pair 11, do nothing

    111001 bit-pair 01, add -7

    bit-pair 00, do nothing

    11101011 -21

ELEC 5200-001/6200-001 Lecture 7


Booth algorithm example 4 l.jpg
Booth Algorithm: Example 4

  • -7 × (-3) = 21

    1001 multiplicand = -7 in two’s com.

    ×1101(0) multiplier = -3 in two’s com.

    00000111 bit-pair 10, add 7

    1111001 bit-pair 01, add -7 in two’s compl.

    000111 bit-pair 10, add 7

    bit-pair 11, do nothing

    00010101 21

ELEC 5200-001/6200-001 Lecture 7


Booth advantage l.jpg
Booth Advantage

Serial addition

Booth algorithm

00010100 20

×00011110 30

00000000

00010100

00010100

00010100

00010100

00000000

00000000

00000000________

000001001011000 600

00010100 20

×00011110 30

111111111101100

00000010100

__________________

0000001001011000 600

Four partial product additions Two partial product additions

ELEC 5200-001/6200-001 Lecture 7


Array multiplier fast l.jpg
Array Multiplier (Fast)

y3 y2 y1 y0 Multiplicand

x3 x2 x1 x0 Multiplier

________________________

x0y3 x0y2 x0y1 x0y0

x1y3 x1y2 x1y1 x1y0 Partial

x2y3 x2y2 x2y1 x2y0 Products

x3y3 x3y2 x3y1 x3y0

__________________________________________________

p7 p6 p5 p4 p3 p2 p1 p0

Note: Carry is added to the next partial product. Adding the carry

from the final stage needs an extra stage.

ELEC 5200-001/6200-001 Lecture 7


Array multiplier l.jpg

y3 y2 y1 y0

Array Multiplier

x0

ppi

yj

0

xi

0

0

0

0

x1

ci

0

FA

x2

co

ppi+1

0

x3

Critical path

FA

FA

FA

FA

0

p2

p1

p0

p7

p6

p5

p4

p3

ELEC 5200-001/6200-001 Lecture 7


Types of array multipliers l.jpg
Types of Array Multipliers

  • Baugh-Wooley Algorithm: Signed product by two’s complement addition or subtraction according to the MSB’s.

  • Booth multiplier algorithm

  • Tree multipliers

  • Reference: N. H. E. Weste and D. Harris, CMOS VLSI Design, A Circuits and Systems Perspective, Third Edition, Boston: Addison-Wesley, 2005.

ELEC 5200-001/6200-001 Lecture 7


Mips multiply instructions l.jpg
MIPS Multiply Instructions

  • Separate 32-bit registers, Hi and Lo, to hold the 64-bit product.

  • Multiply signed:

    mult $s1, $s2 # $s1 × $s2 = Hi, Lo

  • Multiply unsigned:

    multu $s1, $s2 # $s1 × $s2 = Hi, Lo

  • Product is copied into registers by

    • mfhi $s1 # copies Hi into $s1

    • mflo $s1 # copies Lo into $s1

ELEC 5200-001/6200-001 Lecture 7


Binary division unsigned l.jpg
Binary Division (Unsigned)

1 3 Quotient

1 1 / 1 4 7 Divisor / Dividend

1 1

3 7 Partial remainder

3 3

4 Remainder

0 0 0 0 1 1 0 1

1 0 1 1 / 1 0 0 1 0 0 1 0

1 0 1 1

0 0 1 1 1 0

1 0 1 1

0 0 1 1 1 1

1 0 1 1

1 0 0

ELEC 5200-001/6200-001 Lecture 7


Binary division flowchart l.jpg
Binary Division Flowchart

Start

$A=0, $M=Divisor, $Q=Dividend, count=n

$A and $M have

one extra sign bit

beyond 32 bits.

Shift 1-bit left $A, $Q

$A ← $A - $M

No

Yes

$A < 0?

$Q0=0

$R←$R+$M

$Q0=1

Restore $A

(remainder)

count = count - 1

Done

$Q=Quotient

$A= Remainder

No

count = 0?

Yes

ELEC 5200-001/6200-001 Lecture 7


Division l.jpg
Division

33-bit $M (Divisor)

Step 2: Subtract $A←$A-$M

33

33

32 times

33-bit ALU

Initialize

$A←0

Step 1: 1-bit left shift $A and $Q

32

33-bit $A (Remainder)

32-bit $Q (Dividend)

Step 3: If sign-bit ($A)=0, set Q0=1

If sign-bit ($A)=1, set Q0=0 and restore $A

V. C. Hamacher, Z. G. Vranesic and S. G. Zaky, Computer Organization, Fourth Edition,

New York: McGraw-Hill, 1996.

ELEC 5200-001/6200-001 Lecture 7


Example 8 3 2 remainder 2 l.jpg
Example: 8/3 = 2 (Remainder=2)

Initialize $A = 0 0 0 0 0 $Q = 1 0 0 0 $M = 0 0 0 1 1

Step 1, L-shift $A = 0 0 0 0 1 $Q = 0 0 0 ?

Step 2, Add - $M 1 1 1 0 1

$A = 1 1 1 1 0

Step 3, Set Q0 $Q = 0 0 0 0

Restore + $M 0 0 0 1 1

$A = 0 0 0 0 1

Step 1, L-shift $A = 0 0 0 1 0 $Q = 0 0 0 ? $M = 0 0 0 1 1

Step 2, Add - $M 1 1 1 0 1

$A = 1 1 1 1 1

Step 3, Set Q0 $Q = 0 0 0 0

Restore + $M 0 0 0 1 1

$A = 0 0 0 1 0

Cycle 1

Cycle 2

ELEC 5200-001/6200-001 Lecture 7


Example 8 3 2 remainder 2 continued l.jpg
Example: 8/3 = 2 (Remainder=2) (Continued)

$A = 0 0 0 1 0 $Q = 0 0 0 0 $M = 0 0 0 1 1

Step 1, L-shift $A = 0 0 1 0 0 $Q = 0 0 0 ? $M = 0 0 0 1 1

Step 2, Add - $M 1 1 1 0 1

$A = 0 0 0 0 1

Step 3, Set Q0 $Q = 0 0 0 1

Step 1, L-shift $A = 0 0 0 1 0 $Q = 0 0 1 ? $M = 0 0 0 1 1

Step 2, Add - $M 1 1 1 0 1

$A = 1 1 1 1 1

Step 3, Set Q0 $Q = 0 0 1 0

Restore + $M 0 0 0 1 1

$A = 0 0 0 1 0

Cycle 3

Cycle 4

Note “Restore $A” in Steps 1, 2 and 4. This method is known as

the RESTORING DIVISION.

ELEC 5200-001/6200-001 Lecture 7


Non restoring division l.jpg
Non-Restoring Division

  • Avoids the addition in the restore operation – does exactly one add or subtract per cycle.

  • Non-restoring division algorithm:

    • Step 1: Repeat 32 times

      • shift $A, $Q left one bit

      • if sign of $A is 0,

        Subtract, $A ← $A - $M

        else (sign of $A is 1),

        Add, $A ← $A + $M

      • if sign of $A is 0,

        Set Q0 = 1

        else (sign of $A is 1),

        Set Q0 = 0

    • Step 2: (after 32 Step 1 iterations) if sign of $A is 1, add $A ← $A + $M

ELEC 5200-001/6200-001 Lecture 7


Non restoring division 8 3 2 rem 2 l.jpg
Non-Restoring Division: 8/3 = 2 (Rem=2)

Initialize $A = 0 0 0 0 0 $Q = 1 0 0 0 $M = 0 0 0 1 1

Step 1, L-shift $A = 0 0 0 0 1 $Q = 0 0 0 ? $M = 0 0 0 1 1

Subtract - $M 1 1 1 0 1

$A = 1 1 1 1 0 $Q = 0 0 0 0

Step 1, L-shift $A = 1 1 1 0 0 $Q = 0 0 0? $M = 0 0 0 1 1

Add $M 0 0 0 1 1

$A = 1 1 1 1 1 $Q = 0 0 00

Step 1, L-shift $A = 1 1 1 1 0 $Q = 0 0 0 ? $M = 0 0 0 1 1

Add $M 0 0 0 1 1

$A = 0 0 0 0 1 $Q = 0 0 0 1

Step 1, L-shift $A = 0 0 0 1 0 $Q = 0 0 1 ? $M = 0 0 0 1 1

Subtract -$M 1 1 1 0 1

$A = 1 1 1 1 1 $Q = 0 0 1 0

Step 2, Add $A ← $A + $M = 11111+00011 = 00010 (Final remainder)

Cycle 1

Cycle 2

Cycle 3

Cycle 4

ELEC 5200-001/6200-001 Lecture 7


Signed division l.jpg
Signed Division

  • Remember the signs and divide magnitudes.

  • Negate the quotient if the signs of divisor and dividend disagree.

  • There is no other direct division method for signed division.

ELEC 5200-001/6200-001 Lecture 7


Mips division l.jpg
MIPS Division

  • div $s2, $s3 # Lo=quotient, Hi=remainder

  • divu $s2, $s3 # Lo=quotient, Hi=remainder

  • mflo and mfhi retrieve Lo and Hi.

  • Hardware ignores overflow, so software should determine if the quotient is too large.

  • Software should also check if divisor = 0.

ELEC 5200-001/6200-001 Lecture 7