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Reed Solomon Encoder Implementation

Reed Solomon Encoder Implementation. ECE 734 UW-Madison 12/13/00 by Chih-Liang Huang. Big Picture. Design Methodology. Reed Solomon Encoder. Multiplier with Modulo 256. Summary. Test Vector Generator Behavior/functional simulator 8 bits Multiplier with Modulo 256

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Reed Solomon Encoder Implementation

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  1. Reed Solomon Encoder Implementation ECE 734 UW-Madison 12/13/00 by Chih-Liang Huang

  2. Big Picture

  3. Design Methodology

  4. Reed Solomon Encoder

  5. Multiplier with Modulo 256

  6. Summary • Test Vector Generator • Behavior/functional simulator • 8 bits Multiplier with Modulo 256 • VerilogHDL implementation in RTL level • FPGA Express Synthesis

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