The J Computer

1. The J Computer Advay Mengle MIT 6.111, Spring 2007 April 25, 2007

2. The J Computer • Executes Java ME-like bytecode in hardware • Constraints: (relatively) slow clock rate, not much memory • Use Connected, Limited Device Configuration v1.0 • Downloads user-specified class files from PC over RS-232 connection • Interfaces with hardware devices to allow user interaction

3. System Architecture SRAM Main General uP arbitrary backend Specialized uP for Static Class 3 RS-232 Method Bus: control and data Specialized uP for Static Class 1 Specialized uP for Static Class 2 More processors if FPGA size allows arbitrary backend arbitrary backend

4. System Architecture RGB SRAM Main General uP Overlay_Manager VGA_Controller x,y ARGB, oue Specialized uP for Static Graphics Class N overlays N overlays N overlays RS-232 pos, color Method Bus: control and data Specialized uP for Static System Class Specialized uP for Static PS/2 Handler Class More processors if FPGA size allows x,y mouse_clock, mouse_data ps2_frame Mouse_Handler scancode Generic PS2_Handler keybd_clock, keybd_data Keybd_Handler ps2_frame

5. Executing HLLs in Software vs. in Hardware Software VM Native Processor Java Source Java Source javac javac Compiled Compiled Java Bytecode Java Bytecode Verified Interpreted JIT-compiled Executed java (VM)‏ μP Native MC Each bytecode can be one or more native instructions μP Executed

6. General Microprocessor: Simplified to/from SRAM Memory_Manager Bytecode Processing Variable length instructions split into 8-bit “cells”loading, parsing, flow control Class_Manager Parses class files Object_Manager creates and modifies object instances RS_232_UART receives and transmits buffered data to RS-232 to/from desktop bytecode_cell addr init Bytecode _Reader reads bytecode at PC Jump _Control controls PC Invoker calls static or instance methods Method Bus control data Boot controls boot-up bytecode_cell ready jmp_pc en index en reset (to all) SOP_Control setup control signals to all other components Bytecode _to_SOP translation sop raddr1,2 Reg_File 16 regs, 32 bits rdata1,2 SOP (Simple OPeration) Processing 40-bit instructions w/ 8-bit op-code, and either 4 8-bit params or one 32-bit literal computation ready waddr, wen wdata ctl, addr Stack Manager A, B ALU_32 computes arithmetic function of 2 32-bit integers alu_op data Z

7. General Microprocessor: Simplified addr, data, r/w to/from SRAM Memory_Manager Class_Manager Parses class files Object_Manager creates and modifies object instances RS_232_UART receives and transmits buffered data to RS-232 to/from desktop bytecode_cell addr init Bytecode _Reader reads bytecode at PC Jump _Control controls PC Invoker calls static or instance methods Method Bus control data Boot controls boot-up bytecode_cell ready jmp_pc en index en reset (to all) SOP_Control setup control signals to all other components Bytecode _to_SOP maps one or more bytecode cells to one or more SOPs sop raddr1,2 Reg_File 16 regs, 32 bits rdata1,2 ready waddr, wen wdata ctl, addr Stack Manager A, B ALU_32 computes arithmetic function of 2 32-bit integers alu_op data Z

8. Bytecode-to-SOP translation bc[8] ready • Most bytecodes can be directly translated into one or more constant SOPs (looked up in ROM) • Others may generate custom SOPs dynamically Bytecode _to_SOP sop[40] ready bc ready FSM addr empty/full cust sel ROM FIFO >> ready sop[40] sop_in data

9. Goals & Challenges • Final demo: Write MIT Pong in Java • The most complex bytecodes: instanceof, invoke_virtual • Need to traverse type trees • Raise traps via SOP and write in Java, or • Implement via in-BRAM data structures • Gate count • Can we fit 4 processors on a single FPGA?

10. Questions?