Advanced Operating Systems - Spring 2009 Lecture 17 – March 16, 2009

1. Advanced Operating Systems - Spring 2009Lecture 17 – March 16, 2009 • Dan C. Marinescu • Email: dcm@cs.ucf.edu • Office: HEC 439 B. • Office hours: M, Wd 3 – 4:30 PM. • TA: Chen Yu • Email: yuchen@cs.ucf.edu • Office: HEC 354. • Office hours: M, Wd 1.00 – 3:00 PM.

2. Last, Current, Next Lecture • Last time: • M/M/m systems • Scheduling Algorithms • Today • Memory management • Next time: • Caching and Virtual Memory

3. Scheduling algorithms • A scheduling problems is defined by : • The machine environment • A set of side constrains and characteristics • The optimality criterion • Machine environments: • 1  One-machine. • P  Parallel identical machines • Q  Parallel machines of different speeds • R  Parallel unrelated machines • O  Open shop. m specialized machines; a job requires a number of operations each demanding processing by a specific machine • F  Floor shop

4. One-machine environment • n jobs 1,2,….n. • pj amount of time required by job j. • rj  the release time of job j, the time when job j is available for processing. • wj  the weight of job j. • dj due time of job j; time job j should be completed. • A schedule S specifies for each job j which pj units of time are used to process the job. • CSj the completion time of job j under schedule S. • The makespan of S is: CSmax = max CSj • The average completion time is

5. One-machine environment (cont’d) • Average weighted completion time: • Optimality criteria  minimize: • the makespan CSmax • the average completion time : • The average weighted completion time: •  the lateness of job j •  maximum lateness of any job under schedule S. Another optimality criteria, minimize maximum lateness.

6. Priority rules for one machine environment • Theorem: scheduling jobs according to SPT – shortest processing time is optimal for • Theorem: scheduling jobs in non-decreasing order of is optimal for

7. Earliest deadline first (EDF) • Dynamic scheduling algorithm for real-time OS. • When a scheduling event occurs (task finishes, new task released, etc.) the priority queue will be searched for the process closest to its deadline. This process will then be scheduled for execution next. • EDF is an optimal scheduling preemptive algorithm for uniprocessors, in the following sense: if a collection of independent jobs, each characterized by an arrival time, an execution requirement, and a deadline, can be scheduled (by any algorithm) such that all the jobs complete by their deadlines, the EDF will schedule this collection of jobs such that they all complete by their deadlines.

8. EDF The schedulability test for EDF is: In this case U = 1/8 +2/5 + 4/10 = 0.925 = 92.5% It has been proved that the problem of deciding if it is possible to schedule a set of periodic processes is NP-hard if the periodic processes use semaphores to enforce mutual exclusion.

9. Priority Inversion • A high priority process is blocked by a lower priority one. • Example: J1 and J3 share a data structure guarded by a binary semaphore S. • prty(J1) > prty(J2) > prty(J3). • J1 in initiated while J3 is in its critical section • When J1 attempts to enter the critical section it is blocked. • The duration of this blocking cannot be determined as because J3 can be preempted by a higher priority job J2. prty

10. Memory Management • Architectural background • Swapping • Contiguous memory allocation • Paging • Segmentation • Case studies: • The Intel Pentium • Linux

11. Multistep Processing of a User Program

12. Architectural background • Program must be brought (from disk) into memory and placed within a process for it to be run • CPU can access directly only Main memory and registers. • Register access in one CPU clock (or less) • Main memory can take many cycles • Cache sits between main memory and CPU registers

13. Base and limit Registers delimit logical address space • Base register start of logical address space • Limit register end of logical address space

14. Address binding of instructions and data to memory addresses • Absolute code Object code in a form suitable for direct execution. • Relocatable code  Object code that can be run from any memory location. • Compile time If memory location known a priori, absolute code can be generated; must recompile code if starting location changes • Load time Must generate relocatable code if memory location is not known at compile time • Execution time Binding delayed until run time if the process can be moved during its execution from one memory segment to another. Need hardware support for address maps (e.g., base and limitregisters)

15. Logical vs. Physical Address Space • Address space a range of discrete addresses; may correspond to a physical or virtual memory register, a network host, disk sector or other logical or physical entity. • Virtualization of addressing • Logical (virtual) address generated by the CPU • Physical address address seen by the memory unit • A user program deals with logical addresses; it never sees the real physical addresses. • Logical and physical addresses • are the same in compile-time and load-time address-binding schemes • differ in execution-time address-binding scheme

16. Memory-Management Unit (MMU) • Hardware device that maps virtual to physical address • In MMU scheme, the value in the relocation register is added to every address generated by a user process at the time it is sent to memory

17. Dynamic relocation with a relocation register

18. Dynamic Loading • Routine is not loaded until it is called • Better memory-space utilization; unused routine is never loaded • Useful when large amounts of code are needed to handle infrequently occurring cases • No special support from the operating system required; implemented through program design

19. Dynamic linking • Linking postponed until execution time. A stub is used to locate the appropriate memory-resident library routine. Particularly useful for libraries; also known as shared libraries • Stub replaces itself with the address of the routine, and executes the routine • Operating system needed to check if routine is in processes’ memory address.

20. Swapping • Backing store fast disk providing direct access to copies of all memory images for all processes in the system. • Swap out A process moved temporarily out of memory to a backing store. • Swap in The process is brought into memory for continued execution. • Roll out, roll in swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed. • Swap time time to transfer the process, proportional to amount of memory swapped. • Ready queue queue of processes which have memory images on disk and are ready to run. Maintained by the operating system. • Versions of swapping found in UNIX, Linux, and Windows.

21. Swapping

22. Contiguous Allocation • Main memory usually into two partitions: • Resident operating system, usually held in low memory with interrupt vector • User processes then held in high memory • Relocation registers used to protect user processes from each other, and from changing operating-system code and data • Base register contains value of smallest physical address • Limit register contains range of logical addresses – each logical address must be less than the limit register • MMU maps logical address dynamically

23. HW address protection with base and limit registers

24. Multiple-partition contiguous allocation • Hole  block of available memory; holes of various size are scattered throughout memory • When a process is loaded  it is allocated memory from a hole large enough to accommodate it • Operating system maintains information about:a) allocated partitions b) free partitions (hole) OS OS OS OS process 5 process 5 process 5 process 5 process 9 process 9 process 8 process 10 process 2 process 2 process 2 process 2

25. Dynamic storage allocation • First-fit Allocate the first hole that is big enough • Best-fit Allocate the smallest hole that is big enough; must search entire list, unless ordered by size. Produces the smallest leftover hole • Worst-fit Allocate the largest hole; must also search entire list . Produces the largest leftover hole How to satisfy a request of size n from a list of free holes First-fit and best-fit better than worst-fit in terms of speed and storage utilization

26. Fragmentation • External Fragmentation total memory space exists to satisfy a request, but it is not contiguous • Internal Fragmentation allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used • Compaction Reduces external fragmentation: • How  it shuffle memory contents to place all free memory together in one large block • Limits  possible only if relocation is dynamic, done at execution time • I/O problem • Latch job in memory while it is involved in I/O • Do I/O only into OS buffers

27. Noncontiguous logical address space Paging • Frames blocks of physical memory of fixed-size (512 - 8,192 bytes) • Pages  blocks of logical memory of same size. • What the memory management must do: • Keep track of all free frames • To run a program of n pages find n free frames and load program • Set up a page table to translate logical to physical addresses • Address internal fragmentation

28. Dynamic address translation (DAT) • Address generated by CPU is divided into: • Page number (p) – used as an index into a pagetable which contains base address of each page in physical memory • Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit. • For given logical address space 2m and page size2n page number page offset p d m - n n

29. Paging Hardware

30. Mapping logical to physical memory

31. Example 32-byte memory and 4-byte pages

32. Free Frames After allocation Before allocation

33. Page Table • Page table is kept in main memory. • Page-table base register (PTBR) points to the page table • Page-table length register (PRLR) indicates size of the page table • In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction. • Translation look-aside buffers (TLBs) special fast-lookup hardware cache called associative memory. Helps solve the two memory access problem can be solved by the use of a or • Some TLBs storeaddress-space identifiers (ASIDs)in each TLB entry – uniquely identifies each process to provide address-space protection for that process.

34. Associative Memory Page # Frame # • Associative memory – parallel search Address translation (p, d) • If p is in associative register, get frame # out • Otherwise get frame # from page table in memory

35. Dynamic address translation with TLB

36. Effective Access Time • Associative Lookup =  time unit • Assume memory cycle time is 1 microsecond • Hit ratio  percentage of times that a page is found in TLB • Hit ratio =  • Effective Access Time (EAT) EAT = (1 + )  + (2 + )(1 – ) = 2 +  – 

37. Memory Protection • Memory protection protection bit for each frame • Valid-invalid bit attached to each entry in the page table: • valid legal page; the page is in the process’ logical address space. • invalid the page is not in the process’ logical address space

38. Shared Pages • Shared code • One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window systems). • Shared code must appear in same location in the logical address space of all processes • Private code and data • Each process keeps a separate copy of the code and data • The pages for the private code and data can appear anywhere in the logical address space

39. Example

40. Structure of the Page Table • Hierarchical Paging • Hashed Page Tables • Inverted Page Tables

41. Hierarchical Page Tables • Break up the logical address space into multiple page tables • A simple technique is a two-level page table

42. Example • A logical address (on 32-bit machine with 1K page size) is divided into: • a page number consisting of 22 bits • a page offset consisting of 10 bits • Since the page table is paged, the page number is further divided into: • a 12-bit page number • a 10-bit page offset • Thus, a logical address is as follows: • where pi is an index into the outer page table, and p2 is the displacement within the page of the outer page table page number page offset p2 pi d 10 10 12

43. DAT with a two level page table scheme

44. Three-level Paging Scheme

45. Hashed Page Tables • Common when logical address spaces > 32 bits • The virtual page number is hashed into a page table. This page table contains a chain of elements hashing to the same location. • Virtual page numbers are compared in this chain searching for a match. If a match is found, the corresponding physical frame is extracted.

46. Inverted Page Table • One entry for each real page of memory • Entry consists of the virtual address of the page stored in that real memory location and the process that owns that page. • Decreases memory needed to store each page table. • Increases time needed to search the table. • Use hash table to limit the search to one — or at most a few — page-table entries

47. Inverted Page Table

48. Segmentation • Memory-management scheme that supports user view of memory. • Program  collection of segments. • Segment  logical unit such as: main program, procedure, function, method, object, local variables, global variables, common block, stack, symbol table, arrays

49. 1 4 2 3 Logical View of Segmentation 1 2 3 4 user space physical memory space

50. Segmentation Architecture • Logical address <segment-number, offset>, • Segment table maps two-dimensional physical addresses; each table entry has: • base the starting physical address of the segment • limit the length of the segment • Segment-table base register (STBR) points to the segment table’s location in memory • Segment-table length register (STLR) the number of segments used by a program; segment number s is legal if s < STLR