1 / 11

Status report

Status report. 2010/12/3 Atsushi Nukariya. Progress. ・ Progress is as follows. 1. Create software. 2. Add function which receives command from PC. 3. Create data generator which is used in test. Software (1). ・ I added function which sends command to FPGA. ・ Commands are as follows.

Download Presentation

Status report

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Status report 2010/12/3 Atsushi Nukariya

  2. Progress ・ Progress is as follows. 1. Create software. 2. Add function which receives command from PC. 3. Create data generator which is used in test.

  3. Software (1) ・ I added function which sends command to FPGA. ・ Commands are as follows. Command ‘s’ Start/Restart collecting data from FPGA. ‘t’ Stop collecting data from FPGA. ‘q’ Finish collecting data from FPGA. This makes software terminated. ‘r’ Reset FPGA and software.

  4. Software (2) ・ Setup of test is as follows. PC Loopback address (127.0.0.1) Data : 0x20 0xFF Data Sender App GEMFE2 software Command

  5. Software (3) ・ Usage example of command is as follows. Command Reset signal Data Sender App GEMFE2 Software

  6. Software (4) ・ I’m also creating GUI software. ・ Startup screen is as follows. But this is prototype version.

  7. Software (5) ・ Screen when software is running is as follows. ・ Data 0xFF is sent from FPGA. ・ I don’t understand data from FPGA in detail, so this result isn’t related to FPGA’s data.

  8. FPGA (1) ・ GEMFE2’s chip is tested at NiAS. → I only did simulations about FPGA. ・ Clock frequency is adjusted to 1/10. → MCLK : 10 MHz → 1 MHz HCLK : 100 MHz → 10 MHz RCLK : 20 MHz → 2 MHz ・ Create Data Generator on FPGA.

  9. FPGA (2) ・ Create Data Generator on FPGA. → Data 0x061222, 0x200000 are sent repeatedly. ・ Result of simulation is as follows. Output from SiTCP

  10. FPGA (3) ・ I added function which receives command from PC. ・ Setup of simulation is as follows. → After 70 us from start, ‘t’ command is sent. After 100 us from start, ‘s’ command is sent. After 140 us from start, ‘r’ command is sent. After 340 us from start, ‘s’ command is sent.

  11. FPGA (4) ・ Result of simulation is as follows. Start Stop Reset Reset→Configure→WAiT→Transfer Stop Transfer Transfer

More Related