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  1. CS 2204 Spring 2007 Experiment 5 Lab 9

  2. Experiment 5 Lab 9 Outline • Presentation • Digital Design Conventions • Using Digital Product Development • A brief description of Ppm Block 4 and Block 5 • Individual work • Developing non-core circuits of Ppm Block 5 • Using Experiment 5 Design Checks • New handout • Experiment 5 Design Checks CS 2204 Spring 2007

  3. Presentation • Digital Design Conventions • Digital Circuit PrintingConventions • The printout must be readable • Labels, component names, symbols, etc. • If the circuit is large, it must be printed on severalpages • The sheets must be attached to each other • Lines, labels, etc. must be continuous from one sheet to the next CS 2204 Spring 2007

  4. Digital Design Conventions • Digital Circuit PrintingConventions • CS2204 Related • Part 1 of Experiment 5 Design Checks • The team info on the lower right corner is ►Line 1 : the name of the student who designed the schematic + a partner’s name ►Line 2 : partner(s)’ name(s) ►Line 3 : CS2204, Section name, Spring 2007 CS 2204 Spring 2007

  5. Digital Design Conventions • Digital Circuit DrawingConventions • Part 2 of Experiment 5 Design Checks • Remember to beautify the circuit before submitting it • Placecomponents of a (sub)blocknext to each other and separate (sub)blocks from each other • Only horizontal and verticalwires drawn • No unnecessary wire turns • No Unnecessary line tanglings • No need to draw long wires ►One can draw short wires and name them • Components form horizontal and verticalcolumns • Wires are not drawn over components, buffers, pads CS 2204 Spring 2007

  6. Digital Design Conventions • Logic Circuit DesignConventions • Part 3 of Experiment 5 Design Checks • If a component has multipleoutputs, make sure you use the needed ones • Outputs should not be short-circuited unless they are tri-state • If an output is not needed, leave it unconnected CS 2204 Spring 2007

  7. Digital Design Conventions • Logic Circuit DesignConventions • Part 4 of Experiment 5 Design Checks • Do not forget to save schematics • Then, do a Xilinx IMPLEMENTATION to have the changes affect the output • From time to time clear the Implementation data on the Project Manager window by following • Project -> Clear Implementation Data • After clearing the data, next time you do a Xilinx IMPLEMENTATION, reenter the IMPLEMENTATION options CS 2204 Spring 2007

  8. Digital Design Conventions • Logic Circuit DesignConventions • Part 5 of Experiment 5 Design Checks • Perform simulations • If an output value is Hi-Z during simulation, make sure it is correct • Read the Implementation Log file and work on the warnings and errors listed • If you do back to back Xilinx IMPLEMENTATIONs, the new IMPLEMENTATION data is appended to the end CS 2204 Spring 2007

  9. Xilinx Project Development Steps • Develop the schematic • DESIGN the schematic • Design blocks, (sub)blocks • Place the components and wires • Do integrity TESTs • TEST the schematic via functional simulations • MODIFY the schematic to correct an error • Do a Xilinx IMPLEMENTATION • It maps the components to the CLBs of the chip • Do timing simulations to TEST the schematic • It generates the bit file • Download the bit file to the FPGA and test the design on the board • It programs the chip What are these components ? Development Cycle on Computers Development Cycle with FPGA chips CS 2204 Spring 2007

  10. Lab design Use Xilinx macros as much as possible Try not to use these components • CS2204 Components • Available components for a new chip Xilinx components Labs Generic components Lectures, homework, exams Flip-flops Popular digital circuits Gates Flip-flops Popular digital circuits Gates ADDer Comparator Multiplexer DeMux Decoder Encoder ALU Counter Register … AND OR NOT NAND NOR … D JK T SR … ADDer Comparator Multiplexer DeMux Decoder Encoder ALU Counter Register … AND OR NOT NAND NOR … D JK CS 2204 Spring 2007

  11. Designing a New Chip • DESIGN • Implement each circuit • One or more Xilinx Design Blocks, XDBs or Xilinx non-programmablemacros (not gates and FFs) implement the circuit ? A few gates and FFs here and there ? • If yes, draw the schematic and move to the TEST step • One or more Programmable Xilinx macros implement the circuit ? A few gates and FFs here and there ? • If yes, draw the schematic, program the macros and move to the TEST step CS2204 CS 2204 Spring 2007

  12. Designing a New Chip • DESIGN • Implement each circuit • Simple enough to be designed quickly using Switching Theory (less than 5 inputs or less than 5 FFs) so a few gates and/or FFs needed ? • If yes, draw the schematic and move to the TEST step • The circuit can be licensed ? • If yes, borrow it, place it and move to the TEST step • If no to all the above questions, go back to step 1(b) to partition it further or repartition one level up, two levels up,,, or, all the way up CS2204 CS 2204 Spring 2007

  13. The Ppm Term Project • The black-box view • A large number of FFs are used ! • The Ppm is partitioned based on major operations • First partitioning of the digitalsystem • Control Unit • Data Unit • Second partitioning (DataUnit partitioning) • Interfacing to the input/output devices • Handling human player’s play • Controlling display operations based on game rules • Calculating new player points • Determining the machine player play CS 2204 Spring 2007

  14. The Ppm Digital System Partitioning M1 M2 M3 CS 2204 Spring 2007

  15. 26 52 Block 4 • The Ppm Data Unit • Block 4, Play Check Block • It has threemajor operations • Storing the displays, player points and random digit • Position Displays, Points Storage and Random Digit Generation Subblock • Handlingdisplay manipulations • Display Manipulation Subblock • Determiningdisplay digits similar to the digit played • Similar Digit Determination Subblock CS 2204 Spring 2007

  16. 26 52 Block 4 • The Ppm Data Unit • Block 4, Play Check Block CS 2204 Spring 2007

  17. Position Displays, Points Storage & Random Digit Generation Subblock Display Manipulation Subblock Similar Digit Determination Subblock Equal to Lines EQ • The Ppm Data Unit • Block 4, Play Check Block CS 2204 Spring 2007

  18. The Ppm Data Unit • Block 4, Play Check Block • Important outputs of the block • DISP : 16 lines for the position displays • 4 bits each for a display to show the value in Hex • P1PT : 8 lines for the Player 1 points in Unsigned Binary • P2PT : 8 lines for the Player 2 points in Unsigned Binary • RD : 4 lines for the random digit in BCD • PSEL : 4 lines for the position select signals of the current player • It is either P1SEL or P2SEL • ENCPSEL : 2 lines that encode PSEL in Unsigned Binary • BRWD : 4 lines for the digit played and also the minimum reward points that can be earned • EQ : 4 lines one for each display indicating if the corresponding display is equal to the digit played • Pdprd : A single line indicating if the current play resulted in a display overflow CS 2204 Spring 2007

  19. 32 19 Block 5 • The Ppm Data Unit • Block 5, Points Calculation Block • Main goal : calculate the new points for the current player • Experiment 5 targets Block 5 • There are two black boxes, macros, to implement • M1 and M2 How can we implement the block ? CS 2204 Spring 2007

  20. 32 19 Block 5 • The Ppm Data Unit • Block 5, Points Calculation Block • Get pencil and paper • On paperstudy the input/output relationship • 32 inputs and 19 outputs CS 2204 Spring 2007

  21. The Ppm Data Unit • Block 5, Points Calculation Block • Outputs of the block • NSD : 2 bits indicating the adjacency of the current play in Unsigned Binary • The Control Unit uses it to allow the current player to request a random reward or to play again if there is an adjacency • The machine player at the course web site uses it to determine the highest adjacency position • RWD : 8 bits indicating the reward points earned by the current player in Unsigned Binary • The Machine Play Block uses it to make a decision on how to play the random digit • NPT : 8 bits indicating the new points of the current player in Unsigned Binary • The Play Check Block stores it on the corresponding player points register • Ptovf : 1 bit indicating if the current player has exceeded the points limit and so has won the game • It is an overflow bit used by Block 2 to store it on a FF ► Then, the Control Unit uses it the following clock period to stop the game CS 2204 Spring 2007

  22. The Ppm Data Unit • Block 5, Points Calculation Block • There is another major operation left to implement for Ppm : machine playing • These two major operations may need to be tightly coupled if the machine player is highly intelligent • The course web site term project does not tightly couple them ! • A real game chip might have to tightly couple them ! • Block 6 will be discussed next week ! • Block 6 is designed in Experiment 6 CS 2204 Spring 2007

  23. Block 5, Points Calculation Block Development • How can we design Block 5 ? • Try to implement the block immediately • According to the Digital Product Development rules, we need to search the Xilinx component library to see • If this whole block can be implemented by one or more non-programmable macros and perhaps with a few additional gates? ►No, this is not possible ! • If this whole block can be implemented by one or more programmable macros & perhaps with a few additional gates ? ►No, this is not possible ! • If this whole block is simple enough to be implemented by gates right away? ►No, this is not possible ! • Then we have to partition this block into a few subblocks based on the major operations of this block CS 2204 Spring 2007

  24. Block 5, Points Calculation Block Development • Points Calculation Block partitioning • There are several different ways to partition it, one of them is based on the following major operations : • Determine the adjacency of the position played • Determine the reward points of the position played • Determine new player points by adding the reward points to the current player points • Therefore, Block 5 has three subblocks • Adjacency Subblock : core circuit • Reward Calculation Subblock : core circuit • Points Subblock : Macro M1 and Macro M2 CS 2204 Spring 2007

  25. Adjacency NSD Adjacency Subblock Core Core Reward Calculation Subblock Points Subblock Reward Points RWD New Player Points NPT M1 M2 • Block 5, Points Calculation Block Development • Points Calculation Block partitioning CS 2204 Spring 2007

  26. Block 5, Points Calculation Block Development • Points Calculation Block partitioning Adjacency Reward points New player points CS 2204 Spring 2007

  27. Adjacency • Block 5, Points Calculation Block Development • The Adjacency Subblock • Determines the adjacency of the position played • On paperstudy the input/output relationship • 7 inputs and 2 outputs • The adjacency of the position played by the current player is output ►The adjacency is in the Unsigned Binary format • A completely combinational circuit The operation table of the Adjacency Subblock How can we implement the subblock ? CS 2204 Spring 2007

  28. Block 5, Points Calculation Block Development • The Adjacency Subblock • Example for position0 • If EQ1 = EQ2 = EQ3 = 0  NSD = 00 • If EQ1 = 1 & (EQ2 = 0 or EQ3 = 0)  NSD = 01 • If EQ1 = EQ2 = 1 & EQ3 = 0  NSD = 10 • If EQ1 = EQ2 = EQ3 = 1  NSD = 11 Adjacency The operation table of the Adjacency Subblock CS 2204 Spring 2007

  29. Adjacency • Block 5, Points Calculation Block Development • The Adjacency Subblock • Try to implement the subblock immediately • According to the Digital Product Development rules, we need to search the Xilinx component library to see • If this whole subblock can be implemented by one or more non-programmable macros and perhaps with a few additional gates ? ►No, this is not possible ! • If this whole subblock can be implemented by one or more programmable macros and perhaps with a few additional gates ? ►No, this is not possible ! • If this whole subblock is simple enough to be implemented by gates right away ? ►No, this is not possible ! • Then we have to partition this subblock into a few subsubblocks based on the major operations of this subblock CS 2204 Spring 2007

  30. Block 5, Points Calculation Block Development • Adjacency Subblock partitioning • There are several different ways to partition it, one of them is based on the following major operations : • Obtain the unencoded adjacency for all four display from EQ lines • The Adjacent Similar Digits Subsubblock • Select one of them as the unencoded adjacency based on the played position number (ENCPSEL) • The Unencoded Adjacency Subsubblock • Encode the Unencoded adjacency in Unsigned Binary to obtain the encoded adjacency to be used easily by other circuits (NSD) • The Encoded Adjacency Subsubblock CS 2204 Spring 2007

  31. Adjacency • Block 5, Points Calculation Block Development • Adjacency Subblock partitioning Four Unencoded adjacencies Unencoded adjacency of the position played Encoded adjacency of the position played CS 2204 Spring 2007

  32. Block 5, Points Calculation Block Development • Adjacent Similar DigitsSubsubblock • Obtains the unencoded adjacency for all four display from EQ lines • On paperstudy the input/output relationship • 4inputs and 12 outputs • Three outputs show the unencoded adjacency for a display ► They indicate the number of identical adjacent digitsin a row for that position The adjacency information is unencoded Digit played BRWD 2 Display Positions Before the Play DISP 7204 EQ Outputs 0100 From Table 26 How can we implement the subsubblock ? CS 2204 Spring 2007

  33. Block 5, Points Calculation Block Development • Adjacent Similar DigitsSubsubblock • Obtains the unencoded adjacency for all four display from EQ lines • Three outputs show the unencoded adjacency for a display • They indicate the number of identical adjacent digitsin a row for that position ►The adjacency information is unencoded Digit played BRWD 2 Display Positions Before the Play DISP 7204 EQ Outputs 0100 RDP3EQ Outputs RDP3EQ2, RDP3EQ1, RDP3EQ0 100 RDP2EQ Outputs RDP2EQ2, RDP2EQ1, RDP2EQ0 000 RDP1EQ Outputs RDP1EQ2, RDP1EQ1, RDP1EQ0 100 RDP0EQ Outputs RDP0EQ2, RDP0EQ1, RDP0EQ0 000 From Table 26 CS 2204 Spring 2007

  34. Block 5, Points Calculation Block Development • Adjacent Similar DigitsSubsubblock • Try to implement the subsubblock immediately • According to the Digital Product Development rules, we need to search the Xilinx component library to see • If this whole subsubblock can be implemented by one or more non-programmable macros and perhaps with a few additional gates ? ►No, this is not possible ! • If this whole subsubblock can be implemented by one or more programmable macros and perhaps with a few additional gates ? ►Yes, this is possible if we use 12 Xilinx 16x1-bit ROMs One ROM for each output as we will see later in the semester ! This does not seem a simple and quick implementation ! ►Therefore, we decide not to accept this solution ! • If this whole subsubblock is simple enough to be implemented by gates right away ? ►Yes, this is possible since we have only four inputs and we can quickly get the expressions by using textual input/output relationships Our design will have gate networks then ! CS 2204 Spring 2007

  35. RDP3EQ2 RDP3EQ1 RDP3EQ0 • Block 5, Points Calculation Block Development • Adjacent Similar DigitsSubsubblock • Let’s try to get the expressions for the RDP3EQ lines • There is one adjacency if only position 2 is identical to BRWD and so only one line (RDP3EQ2) is 1 • That is if EQ2 = 1, there is one adjacency ►We then say that RDP3EQ2 = EQ2 • There are two adjacencies if position 2AND position 1 are identical to BRWD and so two lines (RDP3EQ2 and RDP3EQ1) are 1 • That’s is if EQ2 = 1 AND EQ1 = 1 ►We then say that RDP3EQ1 = EQ2 EQ1 • There are three adjacencies if position 2AND position 1AND position 0 are identical to BRWD and so three lines (RDP3EQ2, RDP3EQ1 and RDP3EQ0) are 1 • That’s is if EQ2 = 1 AND EQ1 = 1 AND EQ0 = 1 ►We then say that RDP3EQ2 = EQ2 EQ1 EQ0 CS 2204 Spring 2007

  36. RDP3EQ0 = EQ2 EQ1 EQ0 RDP3EQ1 = EQ2 EQ1 RDP3EQ2 = EQ2 • Block 5, Points Calculation Block Development • Adjacent Similar DigitsSubsubblock • The current implementation uses gates and buffers • Buffers are used to rename wires • Xilinx does not allow giving multiple names to a wire Circuit for RDP3EQ CS 2204 Spring 2007

  37. Block 5, Points Calculation Block Development • Adjacent Similar DigitsSubsubblock • The current implementation uses gates and buffers • Draw the gates and buffers on paper • Draw the output wires of these components • This will help figure out what to connect to their inputs • Draw inputs of the gates and buffers appropriately • Move the design from paper to the computer • Label the components CS 2204 Spring 2007

  38. Block 5, Points Calculation Block Development • Adjacent Similar DigitsSubsubblock • On paper, after you determine the components to use • ►Draw the components • ► Draw the output wires of the components • ► Draw the input wires of the components Components used 6 Xilinx 2-input AND gates, AND2 6 Xilinx buffers, BUF Total : 12 components used CS 2204 Spring 2007

  39. Block 5, Points Calculation Block Development • Unencoded AdjacencySubsubblock • Selects one of them as the unencoded adjacency based on the played position number (ENCPSEL) • On paperstudy the input/output relationship • 15 inputs and 3 outputs • The adjacency for the played position is output ► The adjacency information is unencoded How can we implement the subsubblock ? CS 2204 Spring 2007

  40. Block 5, Points Calculation Block Development • Unencoded AdjacencySubsubblock • Selects one of them as the unencoded adjacency based on the played position number (ENCPSEL) • The adjacency for the played position is output • The adjacency information is unencoded Digit played BRWD 2 Display Positions Before the Play DISP 7204 RDP3EQ Outputs RDP3EQ2, RDP3EQ1, RDP3EQ0 100 Position played ENCPSEL 3 Digit played is not zero Brwdeqz 0 RDP2EQ Outputs RDP2EQ2, RDP2EQ1, RDP2EQ0 000 Adjacency of Position 3 is output : RDP3EQ UNENCNSD =100 RDP1EQ Outputs RDP1EQ2, RDP1EQ1, RDP1EQ0 100 RDP0EQ Outputs RDP0EQ2, RDP0EQ1, RDP0EQ0 000 CS 2204 Spring 2007

  41. Block 5, Points Calculation Block Development • Unencoded AdjacencySubsubblock • Example for differentENCPSEL combinations • If ENCPSEL is 00 output RDP0EQ • If ENCPSEL is 01 output RDP1EQ • If ENCPSEL is 10 output RDP2EQ • If ENCPSEL is 11 output RDP3EQ • Realize that this is a select (multiplexing) operation • We selectone out of four so it is a 4-to-1 MUX • When we select, we output three bits, so it is a 3-bit 4-to-1 MUX • If Brwdeqz is 1, the outputs are zero • Brwdeqz can be used as the enable/disable signal to the MUXes CS 2204 Spring 2007

  42. Block 5, Points Calculation Block Development • Unencoded AdjacencySubsubblock • Try to implement the subsubblock immediately • According to the Digital Product Development rules, we need to search the Xilinx component library to see • If this whole subblock can be implemented by one or more non-programmable macros and perhaps with a few additional gates ? ► Yes, this is possible ! Table 27. The operation table of the Unencoded Adjacency Subsubblock CS 2204 Spring 2007

  43. Block 5, Points Calculation Block Development • Unencoded AdjacencySubsubblock • According to the Digital Product Development rules, we need to search the Xilinx component library to see if there is such a 3-bit 4-to-1 MUX and if there is not, determine how to implement it with smaller MUXes • No 3-bit 4-to-1 Xilinx MUX, but 2-bit and 1-bit 4-to-1 MUXes • One2-bit 4-to-1 MUX : X74_153 • One1-bit 4-to-1 MUX : M4_1E • Draw the MUXes • Draw the output wires of the MUXes • This will help figure out what to connect to the MUX inputs • Draw Brwdeqz to the Enable inputs of the MUXes appropriately • We need to use an inverter to invert Brwdeqz for one of the MUXes • The M4_E has an active high Enable input ! • Draw the select lines of the MUXes by using ENCPSEL lines • Draw the PDxPRD inputs to the MUX data inputs appropriately • Distribute them to the inputs, do not cluster them ! • Move the design from paper to the computer • Label the components CS 2204 Spring 2007

  44. Block 5, Points Calculation Block Development • Unencoded AdjacencySubsubblock Components used 1 Xilinx inverter, INV 1 Xilinx 4-to-1 MUX, M4_1E 1 Xilinx 2-bit 4-to-1 MUX, X74_153 Total : 3 components used • On paper, after you determine the components to use • ►Draw the components • ► Draw the output wires of the components • ► Draw the input wires of the components CS 2204 Spring 2007

  45. Block 5, Points Calculation Block Development • Encoded AdjacencySubsubblock • Encode the Unencoded adjacency to obtain the encoded adjacency to be used easily by other circuits (NSD) • On paperstudy the input/output relationship • 3 inputs and 2 outputs • The adjacency for the played position is output ►The adjacency information is in the encoded format  The adjacency is in the Unsigned Binary format How can we implement the subsubblock ? CS 2204 Spring 2007

  46. Block 5, Points Calculation Block Development • Encoded AdjacencySubsubblock • Example for differentUNENCNSD combinations • If UNENCNSD is 000 output 00 since there is no1 • If UNENCNSD is 100 output 01 since there is only one1 • If UNENCNSD is 110 output 10 since there are two1s • If UNENCNSD is 111 output 11 since there are three1s • Realize that this is nothing but adding the ones of UNENCNSD ! • How can we add the 1s ? • We can do that by using an adder ! • Since we add three bits, it is a Full Adder ! CS 2204 Spring 2007

  47. Block 5, Points Calculation Block Development • Encoded AdjacencySubsubblock • Try to implement the subsubblock immediately • According to the Digital Product Development rules, we search the Xilinx component library to see • If the whole subsubblock can be implemented by one non-programmable macros and perhaps with a few additional gates ? ►No Full Adder, but 4-bit Adders  We can use a single4-bit Adder as a Full Adder  Xilinx will remove the hardware for the unneeded bits of the Adder CS 2204 Spring 2007

  48. Block 5, Points Calculation Block Development • Encoded AdjacencySubsubblock • Draw the Adder • Draw the output wires to the outputs of the Adder • This will help figure out what to connect to the Adder inputs • Draw UNENCNSD lines to the Adder inputs appropriately • Distribute them to the inputs, do not cluster them ! • Move the design from paper to the computer • Label the component Components used 1 Xilinx 4-bit ADDer, ADD4 Total : 1 component used • On paper, after you determine the component to use • ►Draw the component • ► Draw the output wires of the component • ► Draw the input wires of the component CS 2204 Spring 2007

  49. Block 5, Points Calculation Block Development • The Reward Calculation Subblock • Determines the reward points of the position played • On paperstudy the input/output relationship • 11 inputs and 8 outputs • The reward points for the current player are output ► The reward points is in the Unsigned Binary format Reward points Table 28. The operation table of the Reward Calculation Subblock How can we implement the subblock ? CS 2204 Spring 2007

  50. Block 5, Points Calculation Block Development • The Reward Calculation Subblock • The operation table on the previous slide looks too complex so we get a different looking operation table From Table 29 : A Different Operation Table for the Reward Calculation Subblock. CS 2204 Spring 2007