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IN THE NAME OF GOD

IN THE NAME OF GOD. ADOPTED FROM: IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.41,NO.1,JANUARY 2006 Presented by: Samane Soleimani Amiri Advanced VLSI Course Class presentation. A 146mm 2 8Gb NAND Flash Memory with 70nm CMOS Technology.

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IN THE NAME OF GOD

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  1. IN THE NAME OF GOD ADOPTED FROM: IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.41,NO.1,JANUARY 2006 Presented by: Samane Soleimani Amiri Advanced VLSI Course Class presentation

  2. A 146mm2 8Gb NAND Flash Memory with 70nm CMOS Technology T. Hara1, K. Fukuda1, K. Kanazawa1, N. Shibata1, K. Hosono1, H. Maejima1, M. Nakagawa1, T. Abe1, M. Kojima1, M. Fujiu1, Y. Takeuchi1, K. Amemiya1, M. Morooka1, T. Kamei2, H. Nasu2, K. Kawano2, C. Wang2, K. Sakurai3, N. Tokiwa3, H. Waki3, T. Maruyama1, S. Yoshikawa1, M. Higashitani2, T.D. Pham2, T. Watanabe1 1Toshiba Corporation, Yokohama, Japan 2SanDisk Corporation, Sunnyvale, CA 3Toshiba Microelectronics Corporation, Yokohama, Japan

  3. About NAND Flash Memories • NAND Flash memories have become the key devices for portable mass data storage. • These memories are used in digital still cameras, cellular phones, handheld devices, USB memories, and portable audio and video players. • High memory capacity, and high data throughput.

  4. Outline • Introduction • Chip architecture for small die size • One-sided pad arrangement • Compact memory core design • Block address expansion scheme • MLC program techniques for high throughput • Program with write cache • Vpgm compensation for edge WLs • Device performance • Summary

  5. 100 Digital still camera Portable audio Cellular phone 10 USB memory Unit Die Size (mm2/MB) This Work 1 SLC NAND Flash MLC NAND Flash 0.1 1994 1996 1998 2000 2002 2004 2006 Year Introduction[1]

  6. Two 4Gb memory planes • # of blocks: 2K • Page size: 2KB • Block size: 256KB • # of pages / block: 128 • One-sided pad arrangement and simple memory core design • Half size of pad region • Small wiring area • Short data path ⇒Small die size 4Gb Memory Array (Plane0) 4Gb Memory Array (Plane1) Row decoder Row decoder BL control circuit BL control circuit Charge pump Peripheral circuits Pads Chip Architecture[1]

  7. BLCTRL BLCTRL CELSRC BLS1 CPWEL CPWEL BL selector 1 (BLS1) BL selector 2 (BLS2) Decoder Decoder 4Gb cell array CELSRC CPWEL BLe BLo BL control circuit CELSRC BLS2 BL control circuit Pads Pads Memory Core Design (Conventional) [1]

  8. To realize compact core design with simple power lines and signal wirings • Remove core drivers from the upper side of 4Gb cell array • Merge two BL selectors CPWEL CPWEL CPWEL BL selector 2 (BLS2) BL selector 1 (BLS1) Decoder Decoder Decoder Decoder BLCTRL CELSRC BL control circuit BL control circuit 4Gb cell array 4Gb cell array BL selector (BLS) CELSRC BLCTRL CELSRC Pads Pads Pads Conventional This Work Memory Core Design (This Work) [1]

  9. BLCTRL CELSRC BLS1 CELSRC BLe BLo BLe BLo BLCTRL BLS BLS2 BL control circuit BL control circuit Conventional This Work BL Selector (1) [1]

  10. BLCTRL • No field isolation • Similar M1 connection BLS1 BIASo Cell Array 8 BL pairs BIASe Cell Array 8 BL pairs BLCTRL BLSe BLS BLSo BIASe BLS2 BLSe BLSo BIASo BL control circuit BL control circuit Conventional This Work BL Selector (2) [1]

  11. Conventional This work Block Configuration[1] • Block address expansion scheme • No block redundancy control circuit • No unused “valid” block

  12. 153.0mm2 (100%) - 7.5mm2 (- 4.9%) 145.5mm2 (95.1%) - 7.1mm2 Pad area Power & signal wiring Block R/D control circuit Peripheral circuit - 0.4mm2 BL control circuit Row decoder Cell array Conventional This Work Die Size Reduction[1]

  13. Even Odd BLe_n+1 BLo_n+1 BLe_n BLo_n Upper Lower Lower Upper Lower WLn+1 “0” “1” “0” “1” “0” “1” “0” “1” WLn WLn-1 “X2” “X1” • One WL includes four pages MLC Program[1]

  14. Bit-by-bit verify circuit VREG DTG Latch<B> BLPRE REG BLCLAMP BLCB BLo BLe (2) Lower page program (1) Transfer Latch<A> / IO CSL BLCA IO (0) Data load (N) (3) Data load (N+1) MLC Program (Lower page) [1]

  15. Bit-by-bit verify circuit VREG DTG Latch<B> BLPRE REG BLCLAMP BLCB BLo BLe (6) Upper page program (4) Transfer Latch<A> (5) Lower page read / IO CSL BLCA IO (3) Data load (N+1) (7) Data load (N+2) MLC Program (Upper page) [1]

  16. Program Voltage Compensation • The program time depends on the number of program pulses. • The coupling ratio of floating gate is different in each WL. • If the coupling ratio of WL 0 and 31 are higher than the others, the program speed of WL 0 and 31 becomes faster. • If the program start voltages for other WLs are set higher, the total numbers of program pulses become small and program speed becomes faster.

  17. Voffset WL1~30 WL1~30 WL0, 31 Voffset Number of Cells DVPGM WL0, 31 Vth Distribution (Single pulse program) Program Voltage C0 < C1 WL SGS 0 1 2 29 30 31 SGD C0 C1 C1 C1 C1 C0 N+ N+ Pwell Program Loops Vpgm Compensation[1]

  18. Average program time: 670ms Program time = (Upper page prog. + Lower page prog.) / 2 60 50 40 30 Frequency (%) 20 10 0 Program Time (ms) Program Time[1]

  19. tPROG=670ms, tWC=30ns 7 x8 I/O 6 Write cache & Vpgm compensation +30% 5 Program Throughput (MB/s) 4 3 Without write cache & Vpgm compensation 2 0 0 2 4 Page Length (KB) Program Throughput[1]

  20. Condition: 85℃, Cload=50pF tREA tRC (tRP=15ns) 2.7V 16.5ns 2.7V 23.0ns Shmoo Plot[1]

  21. Features Technology 70nm p-sub triple-well CMOS 3-metal (1W, 2Al) Cell size 0.024mm2 (effective) Die size 145.5mm2 Organization 2112 x 128 page x 4K block x 8 1056 x 128 page x 4K block x 16 Power supply 2.7~3.6V Read cycle 50ns (Normal: 100pF) 30ns (Burst: 50pF) Write cycle 30ns Prog. throughput 6MB/s Read throughput 30MB/s (X8) 60MB/s (X16)

  22. Summary • 70nm 8Gb NAND Flash memory • Small die size: 146mm2 • One-sided pad arrangement • Compact memory core design • Block address expansion scheme • Fast MLC program throughput: 6MB/s • Program with write cache • Vpgm compensation for edge WLs

  23. Reference [1]. T. Hara1, et “A 146mm2 8Gb NAND Flash Memory with 70nm CMOS Technology” IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.41,NO.1,JANUARY 2006

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