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IEEE 1394

CASI / ELEC 98. IEEE 1394. A high-speed computer I/O serial bus. By Rachad ALAO Ecole Nationale Supérieure des Télécommunications ralao@venus.org. What’s the best way to interconnect these devices ?. Video Camera. PC. DVD - RAM. IEEE 1394, by Rachad ALAO ( ralao@venus.org ).

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IEEE 1394

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  1. CASI / ELEC 98 IEEE 1394 A high-speed computer I/O serial bus By Rachad ALAO Ecole Nationale Supérieure des Télécommunications ralao@venus.org

  2. What’s the best way to interconnect these devices ? Video Camera PC DVD - RAM IEEE 1394, by Rachad ALAO ( ralao@venus.org )

  3. What’s the best way to interconnect these devices ? Isochronous Traffic. Bandwidth Requirement : 6Mbit/s Video Camera PC DVD - RAM Sporadic traffic. Bandwidth Requirement : 16Mbit/s • Why not with USB? Too slow! • Why not with a SCSI bus? Fast enough, but… • What about an IEEE1394 bus? You’ve got it! IEEE 1394, by Rachad ALAO ( ralao@venus.org )

  4. IEEE 1394 Lecture Plan • I. How does IEEE 1394 work ? • Overview • Topology • Type of Transaction • Protocol’s Structure • Example of Data Transfer • II. Architecture of a IEEE 1394 Controller. • Project Overview • Functional Block Overview • Block Level Detailed Architecture • Transaction Layer, driver. • III. Conclusion. IEEE 1394, by Rachad ALAO ( ralao@venus.org )

  5. How does IEEE 1394 work ? Overview • High Speed • Hot plug and play • Isochronous capable • “Memory-bus-like” logical architecture Back to Lecture Plan IEEE 1394, by Rachad ALAO ( ralao@venus.org )

  6. How does IEEE 1394 work ? Topology • Physical topology is a non-cyclic network but Logical Topology is a bus. • Node_ID[ 15 .. 0] = Bus_ID[15 .. 6] || Physical_ID[ 5 .. 0] Back to Lecture Plan IEEE 1394, by Rachad ALAO ( ralao@venus.org )

  7. How does IEEE 1394 work ? Type of Transaction • Different type of subaction : • Asynchronous subaction • Asynchronous broadcast subaction • Isochronous subaction • Different part of a subaction : • Arbitration sequence • Data packet • Acknowledgment Typical structure of a data packet Back to Lecture Plan IEEE 1394, by Rachad ALAO ( ralao@venus.org )

  8. How does IEEE 1394 work ? Protocol’s Structure • Different managers needed : • ROOT ( Arbiter ) • CYCLE_MASTER • ISOCHRONOUS MANAGER • BUS MANAGER Back to Lecture Plan IEEE 1394, by Rachad ALAO ( ralao@venus.org )

  9. How does IEEE 1394 work ? Example of Data Transfer 1 Video Camera Node_ID = 1 PC DVD - RAM Root Isochronous Manager Bus Manager Cycle Master Node_ID = 3 Node_ID = 2 Back to Lecture Plan IEEE 1394, by Rachad ALAO ( ralao@venus.org )

  10. How does IEEE 1394 work ? Example of Data Transfer 2 DVD RAM want to perform a write data block transaction to the PC Isochronous Gap Subaction Gap • Step 1 : Cycle_Start Ch. i Ch. j Arbitration TX_DATA_END • Step 2, 3, 4 : Cycle_Start Ch. i Ch. j Data Packet Acknowledge Gap • Step 5 : Cycle_Start Ch. i Ch. j Data Packet Acknowledge Packet Back to Lecture Plan IEEE 1394, by Rachad ALAO ( ralao@venus.org )

  11. How does IEEE 1394 work ? Example of Data Transfer 3 Camera sends MPEG2 data to the PC at a 6 Mbit/s fixed rate. • Prior to all its isochronous transfers, the camera must allocates bandwidth and channel. Isochronous Gap Cycle_Start • Step 1 : Arbitration TX_DATA_END Cycle_Start Ch. K Data Packet • Step 2, 3, 4 : Back to Lecture Plan IEEE 1394, by Rachad ALAO ( ralao@venus.org )

  12. Architecture of a IEEE 1394 Controller Project Overview Back to Lecture Plan IEEE 1394, by Rachad ALAO ( ralao@venus.org )

  13. Architecture of a IEEE 1394 Controller Functional Block Overview Receive INT Transmit_Granted FIFO_DS Hold FIFO_R/W Link_request TPA FIFO_Add[7..0] Link_DS Host_DS FIFO_Data[31..0] R/W R/W TPB Link Layer Phy Layer Add[7..0] Host_Add[7..0] Link_DS Local Host Bus Adapter * FIFO Controller Link_Data[7..0] Host_Data[31..0] Link_R/W Power Phy_DS Link_Add[2..0] FIFO_DS Phy_Data[7..0] Link_Data[31..0] FIFO_Data[31..0] Clk ( 50 Mhz ) Clk ( 50 Mhz ) Link_On /Reset Clk ( 33 Mhz ) Power_Down /Reset /Reset * Local Bus Adapter Interface is Bus Dependent! No generic interface can be given. Transaction layer and part of the bus management will be software components ( driver ) Back to Lecture Plan IEEE 1394, by Rachad ALAO ( ralao@venus.org )

  14. Architecture of a IEEE 1394 Controller Block Level Detailed Architecture - PHY Receive Transmit Data Encoder Transmit_Granted Hold Link_request TPA Link_DS Cable Analog Interface Phy State Machine & Internal Regs R/W Add[7..0] TPB Link_Data[7..0] Phy_DS Power Phy_Data[7..0] Clk ( 50 Mhz ) Receive Data Decoder Link_On Power_Down /Reset Back to Lecture Plan IEEE 1394, by Rachad ALAO ( ralao@venus.org )

  15. Architecture of a IEEE 1394 Controller Block Level Detailed Architecture - LINK Receive CRC Transmit_Granted Transmitter FIFO_DS Isoch. Manager Hold FIFO_R/W Link_request FIFO_Add[7..0] Link_DS FIFO_Data[31..0] R/W Link State Machine and Registers Add[7..0] Link_DS Phy Interface Link_Data[7..0] Link_R/W Link_Add[2..0] Phy_DS Phy_Data[7..0] Link_Data[31..0] Isoch. Monitor Clk ( 50 Mhz ) Clk ( 50 Mhz ) Receiver Link_On /Reset Power_Down CRC /Reset Back to Lecture Plan IEEE 1394, by Rachad ALAO ( ralao@venus.org )

  16. Architecture of a IEEE 1394 Controller Block Level Detailed Architecture - FIFO INT FIFO Controller &Internal Regs FIFO_DS FIFO_R/W FIFO_Add[7..0] FIFO_Data[31..0] Host_DS R/W Link_DS Host_Add[7..0] Link_R/W General Receive FIFO Host_Data[31..0] Link_Add[2..0] FIFO_DS Link_Data[31..0] Link Layer Interface Host Adapter Interface FIFO_Data[31..0] Asynch. Transmit FIFO Clk ( 50 Mhz ) /Reset Clk ( 33 Mhz ) Isoch. Transmit FIFO /Reset Back to Lecture Plan IEEE 1394, by Rachad ALAO ( ralao@venus.org )

  17. Architecture of a IEEE 1394 Controller • Transaction Layer, driver • The Transaction layer and part of the bus management functions • must be software components. • Transaction layer must implement Read, Write and Lock transaction. • Driver must offer ability to handle isochronous transfer. • Driver must be IRQ driven and able to initiate DMA transfers. • Driver model will depend on the target application OS. Back to Lecture Plan IEEE 1394, by Rachad ALAO ( ralao@venus.org )

  18. Conclusion • Objectives : • Give a synthesis of the IEEE 1394 Bus standard • Give a Hardware Specifications of an IEEE 1394 Solution • Constitute a good starting for the development of an IEEE 1394 Solution • Reached ! • + Gave me a good understanding of the IEEE 1394 Protocol • -Showed me the difficulty to build specifications from a complex standard • - No multicast for asynchronous packets! Surprising for such a complicated • standard. Back to Lecture Plan IEEE 1394, by Rachad ALAO ( ralao@venus.org )

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