James Mooney, Simon Effler, Mark Halton, Hussain Mahdi University of Limerick james.mooney@ul.ie

1. Interrupt Controller for DSP-based Control of Multi-Rail DC-DC Converters with Non-Integer Switching Frequency Ratio James Mooney, Simon Effler, Mark Halton, Hussain Mahdi University of Limerick james.mooney@ul.ie 15/12/2010

2. Overview • Introduction to DSP-based Control of Multi-Rail DC-DC Converter Systems • Interrupt Management for Multiple Control Loops • Modified Interrupt Controller • Multi-rail DC-DC Converter Application • Conclusions

3. DSP-based Control of Multi-Rail DC-DC Converter Systems • Multiple DC-DC converters are compensated by a single DSP-based digital controller • An interrupt signal triggers execution of a control algorithm when a new ADC sample is available

4. Interrupt-Triggered Control With Integer Multiple Frequency Ratios • For multiple converters interrupt signals are interleaved so that each control loop’s interrupt service routine has a fixed time slot • Constraining switching frequencies to integer multiples of each other can impact efficiency or performance of converters

5. Interrupt-Triggered Control With Non-Integer Multiple Frequency Ratios • A delay in the calculation and updating of the duty cycle for at least one converter will occur if: • An interrupt is triggered when a control algorithm is already being executed • Multiple interrupt signals are triggered simultaneously • The delay can vary each time an interrupt is triggered

6. Interrupt-Triggered Control With Non-Integer Multiple Frequency Ratios • If duty cycle has not been calculated by beginning of next switching cycle, DPWM will apply duty cycle from previous cycle • If load transient occurs: • Duty cycle update delay will result in slower response in output voltage • Instability could occur if delay occurs for a number of consecutive cycles

7. Maximum ADC Sample to Duty Cycle Update Delay • To avoid problems with variable delay, fix delay at maximum for each iteration of each algorithm • For a particular algorithm • Maximum fixed delay is excessive and degrades performance of voltage regulator due to slower response to load transients

8. Modified Interrupt Controller • Modified interrupt controller reduces TDMAX to acceptable value to obtain improved performance: • All interrupts are automatically re-enabled after control algorithm has passed a certain stage of execution • Allows interruption of one algorithm by another during pre-calculation stage, after duty cycle calculation and DPWM updating has been completed

9. Modified Interrupt Controller • Improved interrupt scheme can be achieved by augmenting a conventional DSP’s interrupt controller with minimal additional hardware: • Counter that determines when to re-enable interrupts • Registers to store interrupt return addresses and duty-cycle calculation times for each algorithm in terms of number of instructions required

10. Multi-Rail DC-DC Converter Application • FPGA Implementation • Dual Datapath DSP core with modified interrupt controller • Multi-rail switching mode power supply system • 3 buck converters • 12V – to – 1.5 V • 500 & 495 kHz switching frequencies • 3rd order linear compensator applied to each converter • 6 duty-cycle operations • 6 pre-calculation operations

11. Interrupt Controller Operation - Comparison Standard Modified

12. Interrupt Controller Operation - Standard • Int0 triggered • Int1 triggered • ISR0 executed • ISR1 executed

13. Interrupt Controller Operation - Comparison Standard Modified

14. Interrupt Controller Operation - Modified • Int0 triggered • Int1 triggered • ISR0 started • ISR0 duty cycle calculation completed • ISR1 executed • Remainder of ISR0 executed

15. Performance Comparison Standard Modified • Modified interrupt method has shorter TDMAX delay • This facilitates the use of a wider bandwidth compensator • Result: Improved performance in response to load step

16. Conclusions • Drawback of a standard DSP controlling multiple power converters is its limitation in dealing with switching frequencies with non-integer ratios • ADC-sample to duty-cycle-update delay • Existing DSPs have excessive delay • Proposed method has a constant, reduced and hence more desirable delay • Proposed interrupt controller performs significantly better in non-integer switching frequency applications • Demonstrated using a three-rail power converter prototype

17. Thank you for your attention! Questions? james.mooney@ul.ie

18. Thank you for your attention! Questions? james.mooney@ul.ie

19. Backup Slides

20. Comparison with Standard Interrupt Method • Manually enabling and disabling interrupts

21. Comparison with Standard Interrupt Method • Separate interrupts for duty cycle calculation and pre-calculation code sections

22. Duty cycle updated early in switching cycle

23. Duty cycle updated just in time to be applied