A Framework for the Validation of Processor Architecture Compliance

1. A Framework for the Validation of Processor Architecture Compliance Allon Adir, Sigal Asaf, Laurent Fournier, Itai Jaeger(*), Ofer Peled

2. Processor architecture licensing • Commercial processor architecture licensing drives the need for compliance validation • Architecture owners must prevent fragmentation of the architecture • Licensees would like to make sure their design is compatible with existing facilities and software

3. ? ~ Implementation = Compliance validation Functional verification ? ~ Designer’s intent = • Verify that: • Designers have interpreted the architecture correctly • Architecture prescriptions have been followed in a consistent manner Architecture compliance validation Architecture 3

4. When does ‘add’ instruction set the CR bit to zero ? Methods for architecture compliance validation The problem – cont’ • Human interaction based processes • Error prone • Expert effort needed • Legacy architecture compliance test suite • Not systematic • Maintenance issues Developing an Architecture Validation Suite Application to the PowerPC Architecture (Fournier et al., DAC ’99) • Based on a static set of testcases • Covering several ad-hoc coverage models

5. Compliance validation challenges • Provide a comprehensive set of test cases • Covering each and every aspect of the architecture • Make deviation from the architecture observable • Create tests that distinguish wrong behavior from right behavior • Enable easy maintenance • Support different implementations of the same architecture • Effectively cope with architecture evolution

6. Architectural Knowledge Base Architectural Reference Model ACS – an automatic compliance suite generator Back-up pages: The detailed solution Test Test Design Specific Coverage Models Test Test Test Specification Specification Architectural Coverage Models Specification Specification Specification Generator Generator Design Specific PowerPC PowerPC Architectural Knowledge Base Knowledge Base knowledge Base Design Specific Model-basedTest Generator PowerPC PowerPC Reference Model Generator Reference Model Reference Model Architectural - Compliance Test Cases

7. ACS coverage models • Misinterpretation based coverage models • Ambiguity in the text • Oversight of specification portions • Subconscious confusion with a similar, yet different, specification • Internal or external association • Automatically derived from description of • Single instruction behavior • Architectural mechanisms (e.g., translation, interrupts) • Synchronization and multi-processor requirements

8. Implementation decisions • It is common for processor architecture to allow several alternative legal behaviors • Implement vectored instructions? • Take an interrupt on overflow? • A single test may be legal for one implementation of the architecture but illegal for another… • Not all coverage models are applicable to every implementation of the architecture

9. TestSpecification fsel implemented yes External control facility yes Memory size 2^52… The complete ACS system ArchitecturalCoverage Models ACS Defs Generator Architecture Decisions ArchitecturalKnowledge Base Generator Architectural Reference Model Model-based Test Generator Compliance Test Cases

10. Summary • The need for architecture compliance validation is growing • Architecture licensing business models • Complex and evolving architectures pose significant challenges • Current methods are not complete and robust enough • ACS – a system for automatically generating compliance test suites • Comprehensive coverage of misinterpretation models • Automatic generation according to specific implementation choices • Model-based approach addresses architecture evolution

11. Thank you

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13. Misinterpretation flowchart coverage models setOverflow = False setOverflow = True OE=0 OE=1 Mode = 64-bit Mode = 32-bit OE = 1 OE = 0 prec=64 prec=32 32_overflow_occurred = false 64_overflow_occurred = true 32_overflow_occurred = true 64_overflow_occurred = false OE=1 OE=0 OE=0 OE=1 Misinterpretation task: The process goes down a false edge instead of the right edge coming out of the same node

14. Overflow interrupt Arch. 5/0= Divide by zero interrupt Misinterpretations • The concept of misinterpretation constitutes the backbone of the ACS coverage models • Causes for misinterpretations • Ambiguity in the text • Oversight of specification portions • Subconscious confusion with a similar, yet different, specification • Internal association • External association

15. Instruction Operand1 Operand2 fadd fdiv fmul +Zero -Zero +Number -Number +Inf -Inf Nan +Zero -Zero +Number -Number +Inf -Infnan Inst.isRecord=false Inst.isRecord=true CR[0:2] = unchanged MSR[SF] = 1 MSR[SF] = 0 CR[0:2] = 0b010 CR[0:2] = 0b001 CR[0:2] = 0b100 ACS coverage models • The coverage models target misinterpretations of • Single instruction behavior • Architectural mechanisms (e.g., translation, interrupts) • Synchronization and multi-processor requirements • Two types of coverage models are supported: • Flowchart based models • Cross product models