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Advanced Digital Circuit Technology Analysis

Analyzing polysilicon data and implementing P-Network model for RC distributed lines in digital integrated circuits. Solving Elmore delay and Tree RC networks methodology Chapter 4 Problem 4.1.

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Advanced Digital Circuit Technology Analysis

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  1. Τεχνολογία Προηγμένων Ψηφιακών Κυκλωμάτων & ΣυστημάτωνΚαθηγητής: Παπαδόπουλος Γ. Πιτσιώρης Γεώργιος 4830 Ε’ Έτος

  2. Digital Integrated CircuitsJan Rabaey

  3. Chapter 4: Problem 4.1

  4. Δεδομέναγια Polysilicon • Parallel-plate capacitance to substrate: 0.088 fF/μm2 • Fringing capacitance to substrate : 0.054fF/μm • Sheet resistance : 4 Ω/sq

  5. Ιav= Ctotal* ΔV/ΔT= =(4*100fF+7*Cws)*5Volts/5nsec= =400fF+7*(5mm*3μm*0.088fF/μm2 +2*5mm*0.054fF/μm)Volts/nsec= =400fF+7*(1320fF+540fF)Volts/nsec= =13.42mA Iav,90%=0.9*13.42mA=12.078mA

  6. Π-Network model για RC distributed Line

  7. Έτσι διαμορφώνεται το ισοδύναμο κύκλωμα

  8. Capacitors : Cws=5mm*3μm*0.088fF/μm2+2*5mm* 0.054fF/μm=(1320+540)fF=1860fF • Resistors : Rws=5mm/3μm*4Ω/sq=6.67kΩ

  9. Το dominant time constant είναι το elmore delay (first order time constant) • Penfield-Rubenstein-Horowitz δίνουν μεθοδολογία για tree RC networks • τ=1.5* Cws*(Rws+Rws+2*Rws)+(0.5*Cws+100fF)* (Rws+Rws+2*Rws+3*Rws)=9.5*Cws*Rws+7*Rws*100fF= 9.5*1860fF*6.67kΩ+7*100fF*6.67kΩ=122.528nsec

  10. Λύση με άλλα δεδομένα • Parallel-plate capacitance to substrate: 0.058 fF/μm2 • Fringing capacitance to substrate : 0.043fF/μm • Sheet resistance : 4 Ω/sq

  11. Αποτελέσματα • Ιav= Ctotal* ΔV/ΔT= =(4*100fF+7*Cws)*5Volts/5nsec= =400fF+7*(5mm*3μm*0.058fF/μm2 +2*5mm*0.043fF/μm)Volts/nsec= =400fF+7*(870fF+430fF)Volts/nsec= =9.5mA • Iav,90%=0.9*9.5mA=8.55mA

  12. Αποτελέσματα • Capacitors : Cws=(870+430)fF=1300fF • Resistors : Rws=5mm/3μm*4Ω/sq=6.67kΩ • τ=1.5* Cws*(Rws+Rws+2*Rws)+(0.5*Cws+100fF)* (Rws+Rws+2*Rws+3*Rws)=9.5*Cws*Rws+7*Rws*100fF= 9.5*1300fF*6.67kΩ+7*100fF*6.67kΩ=87nsec

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