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Chapter 12

Chapter 12. Interrupts. Interrupts. What is an interrupt?  A hardware-initiated subroutine call  This gives the hardware access to software  No interaction occurs until the hardware wants the software to perform some function

nicholas-madden
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Chapter 12

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  1. Chapter 12 Interrupts

  2. Interrupts • What is an interrupt?  A hardware-initiated subroutine call  This gives the hardware access to software  No interaction occurs until the hardware wants the software to perform some function • An interrupt service procedure/routine (ISP or ISR) is the subroutine called for execution by the hardware interrupt.

  3. Hardware in a personal computer and most embedded systems use the interrupt structure extensively. • Interrupts provide a more efficient alternative to polling as a way to interface processor to slow devices Processor does useful things rather than waits Printer ISR Executed Keyboard ISR Executed

  4. Hardware Interrupts • INTR & NMI Hardware inputs • #INTA Hardware ACK for INTR interrupts only • IF (Interrupt Flag) enables/disables INTR interrupts • For INTR, interrupt number n supplied to the processor by the interrupting hardware in an INTA read cycle • For NMI: n = fixed at 2 Software Interrupts • INT n Instruction, n = interrupt number: • Special cases:  n = 1: Single step (trap) Enabled if TF (Trap flag) bit in Flags is set  n = 3: INT 3 (Breakpoint)  n = 4: INTO (Overflow)  n = 5: BOUND (Check limits) For both: • ISR ends with the IRET Instruction to return from interrupt Conditional

  5. Interrupt Vectors/Descriptors • The location of each ISR program (Interrupt Service Routine) in memory is stored in an interrupt vector/descriptor table: - In the real mode: As a 4-byte far address (to specify a segment and an offset) - In the protected mode: As an 8-byte interrupt descriptor • A total of 256 different interrupt type numbers for software and hardware interrupts • ISRs are identified by the interrupt type numbers (0-255d) • Stored in: (use interrupt number as a pointer to determine interrupt vector/descriptor)  Real Mode: The first 1024 B of RAM (256 x 4 B) at the bottom of the memory map (for the 8086: 00000-003FF)  Protected Mode: In the interrupt descriptor table (IDT) (2 KB = 256 x 8B) • How does the processor know the interrupt number?: - Software interrupts: Using the xx in the INT xx instruction - INTR Hardware interrupts: Interrupting device places the vector number (xx) on the data bus in response to the interrupt acknowledge (#INTA) - NMI is treated as a software interrupt (its xx = 2 is fixed & known to the processor)

  6. Software Interrupts • Conditional: - INTO (interrupt type 4): on Overflow (the OF flag bit) - BOUND (type 5): on the result of comparing the contents of a register with the contents of two successive words in memory, e.g. BOUND AX, DATA causes interrupt type 5 if AX contents are outside the range specified by the 4 bytes i.e., [AX] < {[DATA], [DATA+1]} or [AX] > {[DATA+2], [DATA+3]} • Unconditional:  INT n: Executes the interrupt with the vector type n - Instruction takes 2 bytes: a byte for the opcode and a byte for n e.g. INT 80H  Start of the 4-byte vector address = 4 x 80H = 200H (200H – 203H) INT 3: is a special case of INT n which fits into one byte only. Useful in inserting a break point in the software for debugging purposes

  7. Software/Hardware Interrupts • Return from Interrupt (last instruction in the ISR) IRET (instead of RET for returning from subroutine) Retrieves from the stack: - Return address (CS & IP) - The Flags register

  8. Interrupt Vector Table in the Real Mode Top 224 Interrupt Vectors: For user, Hardware and Software First 32 Interrupt Vectors: Reserved for system use 256 Interrupt Vectors Page Fault (Page required is not in Physical memory) Interrupt type number 00H-FFH NMI is internally decoded as Type 2 interrupt. Does not need to provide an external vector like other hardware interrupts Starting address of interrupt vector = 4 n Where n is the vector type 4 bytes Far address for each vector For debugging If Trap flag (TF) F is set 16-bit Segment address 16-bit Offset address

  9. Example 1000 E309 An easy way to multiply by 4 Segment Interrupt Vector for type 41H interrupt Offset

  10. Interrupt Vectors in the Protected Mode • Interrupt Descriptor Table (IDT) : 256 x 8-bytes = 2K B in RAM • Base address of the IDT table is stored in the IDTR register • Address of ISR is defined by a segment selector and a 4-byte offset • DPL: Descriptor Privilege Level • Real mode interrupts can be converted to protected mode interrupts by converting their 4-byte vectors to 8-byte descriptors Interrupt Vector Table in the Protected Mode

  11. Normal Processing ISR 4 5 8 6 Interrupt Processing At the end of every normal instruction, mP checks for interrupts- in this order: 1. Internal Interrupts from results of execution, e.g. overflow, divide by 0 2. Single step 3. NMI 4. INTR 5. INT n instructions Restores original Interrupt status IRET Higher Priority 7 7

  12. When an Interrupt Occurs(Assume Real Mode) 1. The Flags register is pushed onto the stack 2. Both the interrupt (IF) and trap (TF) flags are cleared. This disables the INTR input and the trap from interrupting the interrupt being handled 3. The code segment register (CS) is pushed onto the stack. 4. The instruction pointer (IP) is pushed onto the stack. 5. The interrupt vector contents are fetched from the interrupt vector table and then placed into the IP and CS so that the next instruction executes at the interrupt service procedure addressed by the vector.

  13. Flags • Interrupt flag (I or IF) enables/disables the INTR hardware interrupts • Trace flag (T) turns tracing on or off: Enables/Disables type 1 interrupt (single stepping)

  14. Installing Interrupt 40H .MODEL TINY .CODE .STARTUP JMP START OLD DD ? ;space for saving old vector NEW40 PROC FAR ; ;ISR for INT 40H ; NEW40 ENDP ;start installation START: MOV AX,0 ;will address physical memory segment 0000H MOV DS,AX MOV AX,DS:[100H] ;Load old word from INT 40H offset (40H x 4 = 100H) into AX MOV WORD PTR CS:OLD,AX ;save it into old MOV AX,DS:[102H] ;get INT 40H segment MOV WORD PTR CS:OLD+2,AX ;save it MOV DS:[100H],OFFSET NEW40 ;Load new offset into vector table MOV DS:[102H],CS ;Load new segment into vector table MOV DX,OFFSET START SHR DX,4 ;Divide offset by 16 to get size in paragraphs (16 bytes) INC DX ;Additional paragraph! MOV AX,3100H ;make NEW40 resident by INT 21H ;Invoking DOS function call 21H with AX=3100H ;and DX = size of ISR code (in paragraphs – 16 bytes) ;to keep resident in the CS for execution when interrupt 40H ;arrives END • Saves old vector in OLD and then Loads the interrupt vector for INT 40H Into the vector table • After execution, it leaves the ISR resident in memory by invoking the INT 21H (terminate and stay resident- TSR) • DOS function call Interrupt Vector table is in data segment (DS) 0000H !

  15. Hardware Interrupts Interrupt Pins Internally decoded as type 2 interrupt Usually uses interrupt types numbers 20H to FFH

  16. Non-Maskable Interrupt • The non-maskable interrupt cannot be turned off. • This input is both edge and level sensitive:  Low for a min 2 clock cycles  Then a positive edge  Then high until recognized by the processor • Typical applications: Important system faults, e.g.  Power failure, so that processor can save registers, e.g. into a flash memory

  17. Power to processor does not fall instantly due to large smoothing capacitors in power supply… This gives some time to save things NMI Power failure interrupt to processor CR time constant chosen To give 33 ms output pulse at Q Optical coupling To isolate mains To Retriggerable monostable 60 Hz Square wave (interval = 16.7 ms < Pulse width of 33 ms) i.e. will retrigger the monostable to a give a constant 1 at Q Until a power failure occurs when Q goes low, #Q goes high

  18. INTR and #INTA • The INTR input is a maskable interrupt: Response to it is turned on and off by the interrupt flag using the CLI (off) and STI (on) instructions. • The INTR input is level sensitive and must be held high until recognized. • Placing a logic 1 on the INTR input causes the #INTA output to have a 0-level pulse when interrupt is accepted. • This pulse is normally used by the interrupting device to put the interrupt vector number(type) on the data bus (D0-D7).

  19. The INTR bus cycle Cleared by interrupting device (by hardware) or by ISR Upon acceptance, m P disables further INTRs (Clears IF to 0) At end of ISR, INTR Is re-enabled (IF = 1) (as Flags are Restored by IRET) By processor By interrupting device Device puts the interrupt vector type, n, (1 byte) on the data bus for processor to read

  20. Actions by the interrupting device:1. Raise INTR to the Processor until acknowledged • Devices may produce narrow • pulses as interrupt requests • (suitable only for edge triggering) • But INTR I/P is level • sensitive: • must be kept • high for enough time • for processor • to “see” it 1 mP Clear Prevent interrupts arriving during processor RESET cycle!

  21. Actions by the interrupting device:2. Put Interrupt type number, n, on processor data bus upon #INTA low HiZ unless #G Set type (vector) number 20H-FFH

  22. Chapter 10 followed a handshake (polling) approach Interrupt-driven keyboard interface WK 13 Should be programmed in Mode 1, and INTE bit set to enable interrupts LSB INTR Keyboard IBF PPI: 8255 To mP PC3 interrupts the Processor whenever the Keyboard puts a character in Port A Latch of the PPI Provides interrupt Type upon #INTA low LSB Interrupt Type: 40H

  23. ;An interrupt service procedure that reads a key from ;a keyboard, see Figure 12-12. PORTA EQU 500H CNTR EQU 506H FIFO DB 256 DUP(?) ;queue for received chars in memory INP DD FIFO ;input pointer- set to start of Q initially OUTP DD FIFO ;output pointer- set to start of Q initially KEY PROC FAR USES EAX EBX EDX EDI MOV EBX,CS:INP ;get pointers into EBX and EDI MOV EDI,CS:OUTP INC BL ; .IF BX == DI ;if buffer in memory is full MOV AL,8 ;use command byte B to clear INTE bit MOV DX,CNTR ; OUT DX,AL ;disable 82C55 interrupts… PC4  0 .ELSE ;if not full DEC BL MOV DX,PORTA IN AL,DX ;read key code from port A MOV CS:[BX], AL ;save received key code in memory queue INC BYTE PTR CS:INP .ENDIF IRET KEY ENDP The Keyboard ISR ISR Inc when a char Is added to queue By ISR INP Inc when char removed from queue By other software OUTP

  24. Expanding the Interrupt Structure Will use hardware/software to expand the number of interrupt inputs that can be connected to the processor via the INTR input: Three approaches 1. Hardware: Add a NAND gate for 7 interrupts 2. Software: Daisy chaining of interrupts 3. A Programmable Interrupt Controller (PIC)- the 8259A - for up to 64 interrupts

  25. 1. Additional NAND for 7 interrupts Cct on slide 21 for 1 interrupt (Vector number was fixed) mP (Vector number Now determined by the interrupting line) LSB MSB = 1 7 Interrupt Lines (active low) Any Interrupt 0 1

  26. Interrupt vector numbers for the 7 interrupts MS bit of n is fixed at 1 (see cct) • Table assumes that only one interrupt arrives at any given time on IR lines If multiple IRn lines are activated simultaneously, this generates other vector numbers (not listed); e.g. with IR0 & IR1 on  FCTo resolve priority between two interrupts that are activated simultaneously, we duplicate the ISR for the interrupt having the higher priority at the resulting new vector number 1 • This should be done for all • possible combinations of IRi • (consumes vector space) • Wasteful, but acceptable • in many embedded systems

  27. 2. Daisy Chaining of Interrupts by Software • Better approach – Uses only one interrupt vector (and therefore one ISR) • The hardware will give no direct indication as to the source(s) of the interrupts • So, the ISR itself will determine this by polling the devices taking part in generating the combined interrupt request • The ISR resolves priorities and execute the section of ISR code corresponding to the interrupt of the highest propriety • This is usually done by checking for interrupts in the order of their priority IF IRX IF IRY Which interrupt has Highest priority? IF IRZ

  28. Mode 1 The 4 interrupts combined ORs To Processor Mode 1

  29. ;A procedure that services the daisy-chain interrupt ;of Figure 12-14. C1 EQU 504H ;first 82C55 PPI (where on it? Port …) C2 EQU 604H ;second 82C55 MASK1 EQU 1 ;INTRB 00000001 for PC0 MASK2 EQU 8 ;INTRA 00001000for PC3 POLL PROC FAR USES EAX EDX MOV DX,C1 ;address first 82C55 IN AL,DX TEST AL,MASK1 ;test INTRB (having highest priority) .IF !ZERO? ;Test if PC0 on 1st PPI is 1 ;LEVEL 1 interrupt software here (ISR for INTRB on 1st PPI) .ENDIF TEST AL,MASK2 ;test INTRA .IF !ZERO? ;LEVEL 2 interrupt software here (ISR for INTRA on 1st PPI) .ENDIF MOV DX,C2 ;address second 82C55 TEST AL,MASK1 ;test INTRB .IF !ZERO? ;LEVEL 3 interrupt software here (ISR for INTRB on 2nd PPI) .ENDIF ;LEVEL 4 interrupt software here (ISR for INTRA on 2nd PPI) POLL ENDP Test for interrupts With higher priority first What level? Higher Priority No need to test further - Why?

  30. 8259A: Programmable Interrupt Controller (PIC) • One 8259A expands the INTR interrupt input to an additional 8 vectored, priority encoded interrupt inputs • Nine 8259A (one master + 8 slaves) allow 64 interrupts • Two 8259A programmable interrupt controllers are found in the chip set of a PC.

  31. The 8259A 8 Interrupt Inputs mP Data Bus On-chip addressing: How many addressable registers do we have? Chip Select From address Decoder R/W Control To Processor INTR Outputs/Inputs From master To slaves when Cascading Multiple PICs From Processor #INTA • SP/EN: 2-functon pin • In non-buffered mode SP (Input) : Program as Master/Slave: 1: Master, 0: Salve • In buffered mode: EN (Output): Enable bus transactions in multi-processor system

  32. The 8259A

  33. Using a Single 8259A PIC is slow- so it needs to request Wait states, particularly With recent faster processors SP = 1 (Master) PLD Programmed so that PIC occupies the I/O address range 0400H-0401H

  34. Cascading 8259s:PC Application The Slave Interrupts Through a Master (could have more than one slave) I/O base address: 20H I/O base address: A0H

  35. Basic Operation: Interrupt Control Registers 3. Interrupt being Serviced Register (IS): Bit =1 (Read using OCW3) 1. Interrupt Request Register (IRR): Strobes active requests in (readable using OCW3) Highest 0 0 1 0 0 Default Priority 0 Operation Command Word 0 0 2. Interrupt Mask Register (IMR): Disables (1), Enables (0) Individual interrupt requests (Written & Read using OCW1) Which Interrupt Is being served? What to do at the End Of the current Interrupt:: OCW instructions OCW= Operation Control Word

  36. Handling Interrupt Priority Default Priority Scheme Lower Make lowest What is pending Who is served now At the end of an interrupt processing, the corresponding bit in the IS register should be reset, e.g. with a nonspecific EOI instruction sent at the end of the ISR using an OCW To avoid lower priority interrupts waiting for long times , Following every interrupt service, the priority levels can be rotated such that the level just served becomes the lowest priority level This is achieved by executing a Rotate on nonspecific EOI Instruction by sending the appropriate OCW at the end of the ISR- just before IRET We can arrange for some such operations can be performed automatically by the processor- i.e. not under program control. Priority List Interrupt just Served becomes Lowest priority Through rotation

  37. Programming the PICusing command words (CWs) • Similar to the UART, • We have: • - Initialization programming- using 4 ICWs • Operation programming- using 4 OCWs • Different CWs can use the same I/O address • by following different format • (Similar to command bytes A and B on the PPI)

  38. The 4 ICWs: ICW1 & ICW2 - Always Required ICW1: A0=0 No slaves On-Chip Address bit A0 (not part of the ICW) (Only one PIC – No ICW3 needed) (ICW3 Needed) > 1 PICs Not applicable for 8086-Pentium Use Not applicable for 8086-Pentium Use For all IRi inputs lines • ICW2: • A0=1 • Specifies the MS 5 bits • of 8 contiguous interrupt vector • numbers generated by the PIC, • i.e. it is thebase vector number edcba edcba111 edcba110 …………... edcba000 8 Vectors Base Vector #

  39. Fixed for all 8 vector #s don’t cares

  40. The 4 ICWs: ICW3 & ICW4- Not Always Required Bits indicate if IRi has a slave PIC interrupting on it or not ICW3: A0=1 Required only multiple PICs used To specify if PIC is a master or a slave 3 bits encode the IRi I/P on master to which INTR of the slave PIC goes What happens at end of interrupt? Automatic or not? If not, specify details in OCW2 ICW4: A0=1 Required only if D0 of ICW1 = 1 This is the case for 8086-Pentium Use. Specifies PIC operating modes Buffered/Non-buffered modes Nested operation modes

  41. Summary:Programming the Initialization command words (ICWs) Check D1 on ICW1 (multiple) No need for ICW3 Master Or Slave? Check D0 on ICW1 Always yes For 80X86 family

  42. Programming the Operation command words (OCW1-3) OCW1: Interrupt Mask. Can be Written and Read To load/Read the IMR register set bit to 1 to mask (i.e. disable) corresponding IRi interrupt input = Disable Interrupt (for Writing) IR #, where required- for ‘specific’ Normal EOI or not Rotate or not OCW2: Required only if Normal (not auto) EOI handling was specified in ICW4 Specific IR or not • Reset the IS bit only or Reset it & rotate • Can operate on: •  Default IR (last served) - nonspecific •  A specified IR (in bits L2-L0)- specific • Normal EOI operation or not (Resets IS bit Without rotation) Set the IR specified (by bits L2-L0) To be the lowest priority (not an EOI command)

  43. Programming the Operation command words (OCW1-3) A0 = 0 also for ICW1 and OCW2  Bits D4 D3 make the difference • OCW3: • A0=0 • Read internal registers IR or IS • Polling option • Special mask mode •  The next read operation at the • same I/O address of OCW3 • will output the specified register • (IR or IS) •  The 3rd register (IMR) is read using OCW1

  44. PIC Programming Example: A UART Application 16550 UART To RX From TX PLD Address Decoder for both devices • INTR from UART When: • RX has received a char • TX is ready to get • a char to send • - A modem interrupts • Error condition • (all appear as one here) Decoding starts With A3 Microprocessor 8259 PIC No cascading -Just a single (master) Decoding starts With A1

  45. Enable RX and TX related Interrupts only (RX Ready with Data) 16550 Interrupt Register (ITR) A2 A1 A0 = 001 1 (TX Ready for Data) 0 1 1 1 (RX Errors) The 4 causes lead to the one interrupt- ISR must poll to identify cause! 0 = 07H How?...By reading: The 16550 Interrupt Identification Register (IID) A2 A1 A0 = 010

  46. 16550 Interrupt Identification Register (IID): 4-bit Code identifies Interrupt 6H 4H 2H

  47. ;Initialization software for the 16650 and 8259A ;of the circuit in Figure 12-21 PIC1 EQU 48H ;8259A control A0 = 0 (I/O address) PIC2 EQU 49H ;8259A control A0 = 1 (I/O Address) ICW1 EQU 1BH ;8259A ICW1 (Control Data) ICW2 EQU 80H ;8259A ICW2 (Control Data) ICW4 EQU 3 ;8259A ICW4 (Control Data) OCW1 EQU 0FEH ;8259A OCW1 (Control Data) LINE EQU 43H ;16650 line register (I/O address) LSB EQU 40H ;16650 Baud divisor LSByte (I/O address) MSB EQU 41H ;16650 Baud divisor MSByte (I/O address) FIFO EQU 42H ;16650 FIFO register (write)/IID Register (Read) (I/O address) ITR EQU 41H ;16650 interrupt register (I/O address) INIT PROC NEAR ; ;setup 16650 ; MOV AL,10001010B ;enable Baud rate divisor OUT LINE,AL MOV AL,120 ;program Baud 9600 OUT LSB,AL MOV AL,0 OUT MSB,AL MOV AL,00001010B ;program 7 data, odd OUT LINE,AL ;parity, 1 stop MOV AL,00000111B ;enable transmitter and OUT FIFO,AL ;receiver to operate ; ;Initialization programming for the 8259A ; MOV AL,ICW1 ;program ICW1 OUT PIC1,AL ; A0= 0 MOV AL,ICW2 ;program ICW2 OUT PIC2,AL ; A0= 1 MOV AL,ICW4 ;program ICW4 OUT PIC2,AL ; A0=1 MOV AL,OCW1 ;program OCW1 OUT PIC2,AL ; A0= 1 STI ;enable INTR input on processor ; ;enable 16650 interrupts ; MOV AL,7 OUT ITR,AL;enable interrupt generation from 16550 for RX, TX operation RET INIT ENDP Initialization Programming No need for ICW3 (no cascading) PIC 8259 IMR Enables only IR0 - the IR input we use • The Software: • Initializes both 16550 and 8259 • Enable processor to accept INTR interrupts (set IF to 1) • Enable 16550 to generate interrupts UART Is this the ISR? Covered Before with UART in Ch 11 1BH ICW1 1 1 1 Don’t cares = 0’s 80H ICW3 not needed (Single PIC used) ICW2 ICW4 specifies AUTO EOI- so, no need for OCW2 What is the Vector Number for our interrupt? (we use the IR0 PIC I/P) ICW1 is IRM (enable only IR0)

  48. Operation Programming ISR handles all 16550 interrupts UART generates one interrupt for 4 causes- The UART ISR must Poll (read IDD register) to determine cause of interrupt and Execute relevant portion of ISR code(Interrupt handling by software through daisy chaining) ;Interrupt handler for the 16650 UART of Figure 12-21- UART base address ;is 40H INT80 PROC FAR USES AX BX DI SI IN AL,42H ;read interrupt IDD Register .IF AL == 6 ;handle receiver error .ELSEIF AL == 2 ;handle transmitter ready for data to be sent JMP TRAN ;example 12-13 .ELSEIF AL == 4 ;handle receiver ready with data received JMP RECV ;example 12-11 .ENDIF IRET INT80 ENDP

  49. “Receive” Software: • The ISR RECV part reads a byte from RX buffer on UART • into a memory receive buffer (FIFO) in response to RX interrupt • A program procedure reads a byte from memory buffer (FIFO) • asynchronously to the RX interrupt (when required/feasible) UART Serial Data Received on Serial Link RX Buffer Upon RX Interrupt RECV part of the ISR: Transfers from UART TX buffer to input memory FIFO upon RX interrupt ISR IIN Check for Full Memory Input FIFO 16 K bytes in an Extra segment (ES) Main memory Check for Empty IOUT Program Procedure Asynchronous transfers from memory FIFO to main memory

  50. 1. RECV Portion of the ISR ;RECV portion of the interrupt handler of Example 12-9 RECV: MOV BX,IOUT; get pointers IOUT used for reading from FIFO MOV DI,IIN ; IIN used for writing into FIFO MOV SI,DI INC SI .IF SI == OFFSET FIFO+16*1024 ;If IIN ptr overshot FIFO MOV SI,OFFSET FIFO ;then bring it to beginning .ENDIF .IF SI == BX ;if FIFO full: disable receiver interrupts IN AL,41H ;Read the ITR register AND AL,0FAH ;Modify it to disable RX-related interrupts OUT 41H,AL ;then Rewrite it again .ENDIF IN AL,40H ;read received data from UART STOSB ;Store string byte in AL into ES:DI MOV IIN,SI ;Update IIN in memory MOV AL,20H ;8259A EOI command OUT 48H,AL ;This is a simple “nonspecific EOI” command IRET 16 KB FIFO Size ITR, Address: 41H UART 0 0 40H is the address of the UART RX buffer (Reads) PIC1: This is OCW2 (A0=0)

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