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January 29, 2010 Yokohama, Japan. JEITA – DASC Joint Meeting. Stan Krolikoski January 29, 2010. DASC Overview. Agenda. Call to Order Introductions JEITA standardization activities update by Kojima and Yamamoto-san DASC activities update by Stan Topics

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Presentation Transcript
  • Call to Order
  • Introductions
  • JEITA standardization activities update by Kojima and Yamamoto-san
  • DASC activities update by Stan
  • Topics
    • P1666-System C by Imai-san and Stan
    • P1481-SSPEF by Kanamoto-san
  • AOB
dasc officers
DASC Officers
  • Stan Krolikoski, Cadence, Chair
  • Karen Bartleson, Synopsys, Vice Chair
  • Kathy Werner, Freescale, Secretary
  • Victor Berman, self, Treasurer
dasc standards issued in 2009
DASC Standards Issued in 2009
  • 1450 (OCI)
  • 1481 (OLA)
  • 1685 (IP-XACT)
  • 1800 (SystemVerilog)
  • 1801 (UPF)
  • 1497-2001 SDF is currently in a “reaffirmation Ballot”
ieee p1076 1vhdl ams wg
  • Charter: Revise, maintain and enhance
    • IEEE Std 1076.1: IEEE Standard VHDL Analog and Mixed-Signal Extensions
      • Adds support for continuous time and mixed-signal modeling to VHDL
      • First approved in 1999
      • Maintenance revision approved in 2007
    • IEEE Std 1076.1.1: IEEE Standard VHDL Analog and Mixed-Signal Extensions—Packages for Multiple Energy Domain Support
      • Definitions for electrical, thermal, mechanical, etc. energy domains
      • First approved in 2004
  • Working Group activities in 2009
    • Developed PAR for revision of IEEE Std 1076.1.1
      • Maintenance revision, no new features planned
    • Started planning for next revision of IEEE Std 1076.1
      • Incorporate IEEE Std 1076-2008 changes into IEEE Std 1076.1
      • Enhance language by adding selected new features
  • Planned Working Group activities for 2010
    • Complete revision of IEEE Std 1076.1.1
    • Revision of IEEE Std 1076.1
      • User survey and call for participation (January/February)
      • Complete preliminary planning, develop PAR (March, April)
      • Work on projects identified to be included in the revision (rest of year)
      • Schedule depends on number of participants
  • Contacts:
    • Web site: http://www.eda.org/vhdl-ams
    • WG Chair: Ernst Christen, christen.1858@verizon.net
ieee1647 e wg
IEEE1647 e WG
  • .
  • e Functional verification language standard
  • Currently working towards a 2010 update to the standard
  • Donations received in 2009, now reviewing donations for inclusion.
  • Aiming to complete review process by mid-year.
  • Chair contact: Darren Galpin (Darren.Galpin@infineon.com)
  • Group e-mail: ieee1647@eda.org
ieee p1666 systemc wg
IEEE P1666 SystemC WG
  • Charter is to update the 1666-2005 standard and to add TLM to SystemC standard
  • Goal is to
    • Create/ballot draft P1666-2010 standard in summer 2010
    • Send the approved standard to RevCom by end of 2010
  • PAR was recommended for approval by NesCom on January 22
    • Vote by Standards Board to end on February 4
  • Current discussions with IEEE to bring John Aynsley on board as technical advisor
    • IEEE stands as intermediate between John and OSCI
    • News Flash– contracts very closed to be signed
  • Chair: Stan Krolikoski (stanleyk@cadence.com)
ieee 1685 ip xact wg
  • Group charter
    • Standardize the IP-XACT work done by The SPIRIT Consortium through the IEEE process
  • 2009 milestones
    • Documents prepared for ballot (July)
    • Initial ballot passed with comments (August)
    • Comments address and recirculation ballot passed (September)
    • Package submitted to RevCom and added to December’s agenda for approval (October)
    • RevCom approval (December)
  • 2010 goals
    • Publishing review in progress (January)
    • Standard published (February)
    • Work group’s activities are complete, currently no further work planned
  • Contacts
    • Chairman – Greg.Ehmann@VirageLogic.com
    • Secretary – Gary.Delp@gmail.com

P1699 – Rosetta WG

  • Rosetta: The goal of Rosetta project is to provide language support for true system-level design. The Rosetta view of system level design is centers on the need to bring together information from multiple domains to predict the system-level impacts of local design decisions. In support of this, Rosetta provides mechanisms for defining system-level functional requirements and constraints, defining heterogeneous specifications and specification domains, and composing specifications to define complete systems. Individual specifications are written using semantics and vocabulary appropriate for their domains and composed to define systems. Information from multiple specification domains is composed by defining interactions between them.
  • Charter:
    • Develop a standard for the Rosetta System-Level Specification Language
    • Develop a collection of Rosetta Base Domains for System-Level Specification
    • Broaden the use of System-Level Specification in Electronics Design
  • 2009 Milestones and Activities:
    • Developed a semantics for Transaction Level Specification for state-based systems
    • Developed a semantics for inter-facet synchronization and sequencing
    • Developed initial syntax and semantics for interactions
    • Processed over 500 issues in the standard development database
    • Established an LRM Working Group to manage updates to the standard document
    • Delivered tutorials at ASE and FDL
  • 2010 Plans and Tasks:
    • Update draft LRM to reflect additions and changes from 2009
    • Release the first full draft LRM for discussion in the full Working Group
    • Finalize semantics for facets and interactions
  • For more information:
    • Dr. Perry Alexander, Chair – alex@ittc.ku.edu / +1.785.864.7741
    • Rosetta Web Page – http://www.rosetta-lang.org
    • System-Level Design with Rosetta, Morgan Kaufmann Publishers
    • LRM Working Group meets weekly on Friday afternoons
p1734 quality ip wg
P1734 – Quality IP WG
  • Charter
  • Provide unified quality measurement views
    • Facilitate IP use and integration
    • Facilitate IP improvements
  • Based on VSIA QIP using XML
    • Allows platform portability
    • Facilitates user specific extensions

2009 Accomplishments

  • Completed schema development
  • Developed database for QIP information
    • “Golden” XML extracted from db
    • Completed XML validated against schema
  • Example application developed
    • Validates XML and schema
    • Validates use cases

2010 Plans

  • Complete documentation
  • Release for ballot
  • Re-invigorate participation
    • Engage IP vendors and users for validation


  • kathy.werner@freescale.com
P1735 - Recommended Practice for Encryption and [Use Rights] Management of Electronic Design Intellectual Property (IP)
  • Chartered to reconcile the IP Encryption and Design Protection technologies across the family of DASC sponsored standards through a "Recommended Practices" document, targeted at three communities:
    • IP producers looking for best practices guidance
    • EDA tool providers/users looking for inter-operability
    • Working Groups looking for subject matter experts
  • In 2009 the working group resolved inter-operability issues in IEEE Std1800 and IEEE Std1076.
  • In 2010, the working group expects to address:
    • License management improvements
    • Key Management
    • Rights Management extensions
    • LRM specification improvements
  • Contact:
    • Steven J. Dovich dovich@cadence.com (P1735 chair)
p1800 systemverilog wg
P1800- SystemVerilog WG
  • Charter: To maintain and extend SystemVerilog as a Hardware Design and Verification Language
  • In 2009, IEEE 1800-2009 was approved and released as an official standard
    • Including a merge of IEEE 1364 Verilog into SystemVerilog
    • Enhancements for Assertions
  • In 2010, approval of a new PAR and initial steps in implementation
  • For further information contact
    • ieee1800@eda.org
p1801 design and verification of low power integrated circuits
P1801- Design and Verification ofLow Power Integrated Circuits
  • Scope:
    • The specification of a format to be used in defining the low power design intent for electronic systems and electronic intellectual property. The format provides the ability to specify the supply network, switches, isolation, retention and other aspects relevant to power management of an electronic system. The standard defines the relationship between the low power design specification and the logic design specification captured via other formats (e.g., standard hardware description languages).
    • The standard provides portability of low power design specifications that can be used with a variety of commercial products throughout an electronic system design, analysis, verification and implementation flow.
  • Activities
    • At the end of 2008 the working group finished the final draft, which was balloted and approved in January of 2009. It was released as an IEEE Standard 1801-2009 in March. (http://ieeexplore.ieee.org/servlet/opac?punumber=4809843)
    • The working group resumed meeting with the goal of providing answers to frequently asked questions, interpretations based on the “Sense of the Workgroup” (to be posted at http://www.accellera.org/activities/p1801_upf), and to form the scope of the next version
  • Next version:
    • After collecting *much* user feedback (see contact)
    • Currently projected: 2011-2012.
  • Contact: p1801-chair@lists.accellera.org (Gary Delp, Silver Loon Systems)
p1666 officers
P1666 Officers
  • Stan Krolikoski (OSCI DR) Chair-elect
  • Jerome Cornet (ST DR) Vice Chair-elect
  • Dennis Brophy (Mentor DR) Secretary
p1666 member entities
P1666 Member Entities
  • Accellera
  • Cadence
  • Freescale
  • Intel
  • Mentor
  • NXP
  • OSCI
  • ST Micro
  • Synopsys
  • TI