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OUTLINE Modern MOSFETs: The short-channel effect Source/drain structure Drain-induced barrier lowering Excess current effects Reading : Chapter 19.1, 19.2. Lecture #41. The Short Channel Effect (SCE). |V T | decreases with L Effect is exacerbated by high values of | V DS |

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lecture 41
OUTLINE

Modern MOSFETs:

The short-channel effect

Source/drain structure

Drain-induced barrier lowering

Excess current effects

Reading: Chapter 19.1, 19.2

Lecture #41

EE130 Lecture 41, Slide 1

the short channel effect sce
The Short Channel Effect (SCE)
  • |VT| decreases with L
    • Effect is exacerbated by

high values of |VDS|

  • This is undesirable (i.e. we want to minimize it!) because circuit designers would like VT to be invariant with transistor dimensions and biasing conditions

“VT roll-off”

EE130 Lecture 41, Slide 2

qualitative explanation of sce
Qualitative Explanation of SCE
  • Before an inversion layer forms beneath the gate, the surface of the Si underneath the gate must be depleted (to a depth WT)
  • The source & drain pn junctions assist in depleting the Si underneath the gate
    • Portions of the depletion charge in the channel region are balanced by charge in S/D regions, rather than by charge on the gate
      • less gate charge is required to reach inversion (i.e. |VT | decreases)

EE130 Lecture 41, Slide 3

slide4

depletion

charge

supported

by gate

(simplified

analysis)

VG

n+

n+

depletion region

p

The smaller the L, the greater percentage of charge balanced by the S/D pn junctions:

rj

Small L:

Large L:

S

D

S

D

Depletion charge supported by S/D

Depletion charge supported by S/D

EE130 Lecture 41, Slide 4

first order analysis of sce
The gate supports the depletion charge in the trapezoidal region. This is smaller than the rectangular depletion region underneath the gate, by the factor

This is the factor by which the depletion charge Qdep is reduced from the ideal

One can deduce from simple geometric analysis that

First-Order Analysis of SCE

Wdm

EE130 Lecture 41, Slide 5

v t roll off first order model
VT Roll-Off: First-Order Model
  • Minimize DVT by
  • reducing Toxe
  • reducing rj
  • increasing NA
  • (trade-offs: degraded m, m)
  • MOSFET vertical dimensions should be

scaled along with horizontal dimensions!

EE130 Lecture 41, Slide 6

source and drain structure
To minimize SCE, we want shallow (small rj) S/D regions -- but the parasitic resistance of these regions will increase when rj is reduced.

where r = resistivity of the S/D regions

Shallow S/D “extensions” may be used to effectively reduce rj without increasing the S/D sheet resistance too much

Source and Drain Structure

EE130 Lecture 41, Slide 7

electric field along the channel
Electric Field Along the Channel
  • The lateral electric field peaks at the drain.
    • epeak can be as high as 106 V/cm
  • High E-field causes problems:
    • damage to gate-oxide interface and bulk
    • substrate current due to impact ionization:

EE130 Lecture 41, Slide 8

lightly doped drain structure
Lightly Doped Drain Structure
  • Lower pn junction doping results in lower peak E-field
    • “Hot-carrier” effects reduced
    • Series resistance increased

EE130 Lecture 41, Slide 9

parasitic source drain resistance
Parasitic Source-Drain Resistance

contact metal

dielectric spacer

G

gate

oxide

R

R

s

d

S

D

channel

N

+

source or drain

TiSi2 or NiSi

  • If IDsat0 VGS – VT ,
  • IDsatis reduced by about 15% in a 0.1mm MOSFET.
  • VDsat = VDsat0 + IDsat (Rs + Rd)

EE130 Lecture 41, Slide 10

drain induced barrier lowering dibl
As the source & drain get closer, they become electrostatically coupled, so that the drain bias can affect the potential barrier to carrier flow at the source junction  subthreshold current increases.Drain Induced Barrier Lowering (DIBL)

EE130 Lecture 41, Slide 11

excess current effects
PunchthroughExcess Current Effects

EE130 Lecture 41, Slide 12

slide13
Parasitic BJT action

EE130 Lecture 41, Slide 13

summary mosfet off state vs on state
Summary: MOSFET OFF State vs. ON State
  • OFF state (VGS < VT):
    • IDS is limited by the rate at which carriers diffuse across the source pn junction
    • Sub-threshold swing S, DIBL are issues
  • ON state (VGS > VT):
    • IDS is limited by the rate at which carriers drift across the channel
    • Punchthrough and parasitic BJT effects are of concern at high drain bias
      • IDsat increases rapidly with VDS
    • Parasitic series resistances reduce drive current
      • source resistance RS reduces effective VGS
      • source and drain resistances RS and RD reduce effective VDS

EE130 Lecture 41, Slide 14