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PDP Training (Alexander)

PDP Training (Alexander). Agenda. 1.Explanation of Layout and Function of Circuit Board 2.Operation Explanation per Board 2-1 Drive Description on SMPS 2-2 Operation Explanation of Driving Circuit 2-3 Logic-Main Board 2-4 Scaler Board.

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PDP Training (Alexander)

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  1. PDP Training (Alexander)

  2. Agenda 1.Explanation of Layout and Function of Circuit Board 2.Operation Explanation per Board 2-1 Drive Description on SMPS 2-2 Operation Explanation of Driving Circuit 2-3 Logic-Main Board 2-4 Scaler Board

  3. 1. Explanation of Layout & Function of Circuit Board

  4. [ Function Description by board - 1 ] ■.SMPS(Switching Mode Power Supply) : It is the supplier to provide voltage and current to work the drive voltage and panel in each board. ■.X-MAIN BOARD : It makes the drive wave form by switching FETs to Timing Controlle coming from logic-board and supplies X electrode of panel with the drive wave form via connector. ■.Y-MAIN BOARD : It makes the drive wave form by switching FETs to Timing Controller coming from the logic-board and provides Y electrode of panel with the drive wave form via Scan Driver IC on Y buffer board in order. ■.LOGIC MAIN BOARD : It process image signal and performs buffering of the logic-main board (to create XY drive signal and output) and the address driver output signal. Then it supplies the output signal to the address driver IC(COF Module).

  5. [ Function Description by board - 2 ] ■.LOGIC BUFFER(E,F,G): It delivers the data signal and control signal to the COF. ■.Y-BUFFER (Upper,Lower) : It is the board to impress the scan waveform on the Y board and consist of 2 boards (upper board and lower board). 8 Y-buffers are fixed at the scan driver (STV7617 of STC corp. : 64 or 65 Output). ■.AC Noise Filter : It has functions to remove noise(low frequency) coming from AC LINE and prevent surge. It gives serious effects on the safety regulations (EMC, EMI) according to AC filter. ■.COF(Chip on Flexible) : It impress the Va pulse to the address electrode in the address section and forms the address discharge by electric potential difference with scanning pulse to be dismissed by the Y electrode. It is made in the form of COF and one COF consists of 4 Data Drive IC (STV7610A :96 Output), otherwise single scan is made of 7 COF.

  6. CELL STRUCTURE OF PDP Front panel Bus electrode Dielectric MgO layer ITO electrode Phosphors Barrier Address Electrode Back panel

  7. Electro Arrangement of SD PDP

  8. ADDRESS OPERATION In order to display picture, select the cells.

  9. SUSTAIN OPERATION Display cells through strong Sustain discharge.

  10. 1 SUB-FIELD IMAGE PROCESS (ADS) Reset Address Sustain • Function • Sustain Erase • Wall Charge Set • Issue • Operation margin • Contrast • Short Time • Function • Select On Cell • Issue • High Speed • Low Voltage • Low Failure • Function • Discharge On Cell • Issue • High Efficiency • Low Voltage • ERC Performance

  11. FRAME STRUCTURE (ADS) SF1 SF2 SF3 SF4 SF5 SF6 SF7 SF8 sub-field 1 2 address scan line ..... 1T 2T 4T 8T 16T 32T 64T 128T sustain 480 1TV field (time) Reset Period Address Period Sustain Period D X Y1 Y2 Yn

  12. 1 Picture Structure by 8 sub-field Original Image SF1 SF2 SF3 SF4 SF5 SF6 SF7 SF8 sub-field 1 2 address scan line ..... 1T 2T 4T 8T 16T 32T 64T 128T sustain 480 1TV field (time)

  13. 2. Explanation of Operation per Boards

  14. 1 Picture Structure by 8 sub-field

  15. PIN CONFIGURATION

  16. PIN CONFIGURATION

  17. 2-1. Drive Description on SMPS

  18. Operation Description on SMPS 1. Overview SMPS used in PDP 42" developed into the compact-sized with high efficiency. The asymmetrical half bridge and the flyback converter are applied into all output. To comply with the harmonic restrictions, it takes the power factor improvementcircuit, which converts AC into the high DC and uses as the input of another converter controller. 2. Input controller SMPS works in whole section of AC 90~264V. It is possible to start in the AC 90 and can restart with new input voltage, even in interruption of electric power. STD_5V comes out when AC is impressed 3. Output Controller Given SMPS have 15 output voltages. The following shows the specification of output voltage and output current in case of their successive drive.

  19. Operation Description on SMPS 3-1. Overvoltage protection It has circuit to maintain normal voltage, additionally with circuit for sensing overvoltage, so it means any overvoltage does not give impacts on other output controller.SMPS prevents overvoltage in the latch mode. VS(85V) works protection function more than 100V, over 94V for VA(75V), over 8.2V for D6V, over 4.7V for D3.3V

  20. Operation Description on SMPS 3-2. Short circuit and overvoltage protection It forms definition that in the short circuit of output controller the output impedance is lower than 300mohm. If the VS output have a short circuit in case of given SMPS, SMPS stops its working. Even in the case of short circuit between main output and STD_5V, SMPS does not break down. When the short circuit is removed, it restarts. 4. Detail Description ① AC-DC Converter It converts AC into DC by using the power factor improvementcircuit. This converter was designated to control the high frequency noise, with the function to improve the power factor. This part becomes input controller of another constant-voltage.

  21. Operation Description on SMPS • ② Auxiliary Power • It is the part to supply power of mycom for remote control. When the power is on, it will work, • which means that MICOM is on standby. • This output part is stand_by voltage. When the power-on signal from remote control impress, • it works main power panel of SMPS via stand_by voltage. • ③ Configuration of VS output • Major part of PDF SMPS outputs 85V 5A. It takes asymmetrical half bridge converter and connects • 2 converters with 85V output in parallel, which increases efficiency than one 85V converter, • on the other hand, decreases its size.

  22. Operation Description on SMPS - PWM Part It uses PWM part of ML4824, but there are some points to take cautions. As this part is synchronized with the PFC part, PWM wave in the current mode drive is induced via the current sensor resistance or current transformer, and shows the current flowing in the output controller. ④ DC-DC Converter : Input of VSCAN, VSET and VE belongs to the VS part

  23. Operation Description on SMPS ⑤ Output (VA,Multi Outputs) Pulse

  24. Trouble shooting on SMPS

  25. Trouble shooting on SMPS

  26. 2-2. Operation Explanation of Driving Circuit 1. Overview of Driver Circuit 1) Definition of Driver Circuit The driver circuit division drives the panel with the proper wave form (high voltage pulse) to develop image on the outside terminal division (X electrode group, Y electrode group, Address electrode). High voltage switching pulse is made by MOSFET combination. 2) Working Principle of Driver Circuit To develop image on the PDP, the voltage should be impressed into the X, Y and ADDRESS electrodes (which are component of each pictorial element) under the proper conditions. The driver wave form which is currently applied to is ADS (Address & Display Separate: Driving method to work by dividing address and constant-current section ) Based on this method, the discharge to be done in the pictorial element of PDP can be divided into 3 types as follows. ● Address Discharge: to form the wall voltage within pictorial element by providing lighting pictorial element with information(impressing data voltage) : It is the discharge produced by difference between the positive electric potential of address electrode (normally, Va impressed voltage of 70~75V +Positive Wall charge) and negative electric potential of Y electrode (GND level impression+ Negative Wall charge).

  27. Operation Description on Driving Board ● Constant-current Discharge: It is the display section to form discharge voluntarily with the help of wall voltage formed by address discharge. (It makes optical power to create image) : It is the Self Sustaining Discharge made by combining the electric potential of coherent pulse, normally 160-170Volt, which alternates the X electrode with Y electrode in the sustain section, with the wall voltage according to the pictorial element condition changed by if the former discharge exists or not. That is to say, it works according to Memory characteristic (it means that former working condition defines the current condition) as the basic feature of AC PDP. If the wall voltage formerly exists in the pictorial element(i.e., the pictorial element is on), the discharge makes forms again because the voltage higher than one of the discharging starting time is impressed by combination of the wall voltage and of the next impressed constant-current. While if the wall voltage does not exist in the pictorial element (i.e., the pictorial element is off), the discharge does not form because the voltage could not reach to the level of the discharging starting time, only with constant-current.

  28. Operation Description on Driving Board ● Erasing discharge: To selectively perform the address discharge for respective pixel, pixels of all panels must be on same conditions (same wall charge state and space charge state). Therefore the erasing discharge zone is important factor to obtain driving margins. There are various methods such as application of log waveform but the wall voltage control method by the Ramp Waveform is now widely applied. : The purpose of intialization (Erasing) discharge is to make wall voltage within the the whole of Pixels. In other words, the erasing discharge must make difference between wall voltages uniform depending on whether or not the sustain discharge exists in the previous state. Namely it must remove the wall voltage formed by the sustain discharge and supply ions or elements by causing discharge for removing the wall voltage. In the other words, To remove the wall voltage, limit the time when polarity of the wall voltage is reversely charged by causing discharge or prevent polarity form being reversely charged by supplying appropriate quantity of ions or elements through forming weak discharge [low voltage of erasing]. There are two types of the weak discharge [low voltage]as known so far. 1) Log Waveform adopted by the F-company 2) Weak erasing discharge by the Ramp Waveform largely adopted by Matsushita company, etc. Outside applied voltage is adjusted depending on difference of wall voltage within Pixel, since discharge is formed when the sumof the existing wall voltage remained and the voltage on a rising waveform exceed the driving beginning voltage, by slowly applying the rising slope of the erased waveform for these two methods. In addition, weak discharge is formed since the strength of applied voltage is small.

  29. Operation Description on Driving Board 3) Essential factors for driving board operation - Supplied from power board and the optimum value may somewhat differ from the below cases. ● Vs : 85V - Sustain ● Vset : 60V ~ 70V - Y Rising Ramp ● Ve : 110V - Ve bias ● Vscan : 70V ~ 80V - Scan bias ● Vdd : 3.3V - Logic signal buffer IC ● Vcc : 15V - FET Gate drive IC ● Logic Signal : Supplied from logic board : Gate signal of each FET

  30. Driving Waveform Specification Arrangement

  31. Explanation of Function per Pulse ● Y Rising Ramp Pulse Outside voltage of about 390V~400V is applied to the Y electrode in the Y Rising Ramp zone, and weak discharge begins if respective gap voltage equals to the discharge beginning voltage. Negative Wall charges accumulate on the Y electrode and the Positive Wall charges on the X electrode in the whole while weak discharge is maintained. ● Y Falling Ramp Pulse Most of Negative Wall charges accumulated on the Y electrode by the X bias of about 200V are used to remove Positive Wall charges in the Y Falling Ramp zone, and most of Positive charges accumulated on the (0V) Rising Ramp zone toward the address electrode are maintained, having distribution of wall charges beneficial for the subsequent address discharge.

  32. Explanation of Function per Pulse ● Y Scan Pulse Y scan pulse is called as injection pulse, and selects the Y electrode one by one (Line-at-a-time). In this case, Vscan is called as Scan bias. For the electrode line with the Vscan voltage applied, voltage of about 70 Volt (Vscan) is applied, and voltage of 0 Volt(GN0) is applied. However, since Negative Wall charges accumulate on the Y electrode by the application of Ramp pulse and Positive Wall charges accumulate on the address electrode, voltage of more than the discharge beginning voltage is applied to the cell where address pulse(70V~75V) is allotted and thus address discharge occurs. Address time of the PDP is very long since both scan pulse and data pulse must be applied in line at a time. ● 1st Sustain Pulse The Sustain Pulse always begins from the Y electrode, it is because Positive Wall charges are formed on the Y electrode if address discharge occurs. The wall charges formed by the address discharge are less than those for the sustain discharge, and thus the strength of the initial discharge is weak. Sustain discharge usually become stable after 5~6 times of discharge depending on structure of electrode and environment. Therefore, the initial long sustain pulse is intended to form the initial discharge stable and form the wall charges much as possible as.

  33. 1. Y buffer - To check whether there is failure of the Y Main, firstly check normal operation of the Y buffer. - After separating both the Y Main and the Y buffer connector, - Check forward voltage drop of 0.4V ~ 0.5V by diode check between OUTL and OUTH. - In addition, resistance between both ends is also more than several kΩ. Trouble shooting on Driving Board

  34. Trouble shooting on Driving Board 2. Y Main - After connecting both the Y Main and the Y buffer, check that output of one of OUT1~8 of the Y buffer is done as follows in application of power

  35. Trouble shooting on Driving Board 3. X Main - Check output of the TPOUT on the X board is done as follows in application of power

  36. 2-3. Operation Explanation of Logic Board

  37. Definition of Name and Terms on Logic Board

  38. Explanation of Logic Board Logic board is composed of a logic main board that generates and outputs the address driver output signal and the XY driving signal by processing image signal, and a buffer board that buffers the address driver output signal and delivers it to the address driver IC (COF Module).

  39. 2-4. Explanation of Scaler(Image Board) Operation

  40. Explanation of Scaler(Image Board) Operation

  41. Factory Data per each Mode 1. UPD 64083 (COMB FILTER) 2. VPC 3230(M) : Main VCD

  42. Factory Data per each Mode 3. VPC 3230(S) : SUB VCD 4. FLI 2200 (De-Interlacer)

  43. Factory Data per each Mode 5. ASI500 Ⅰ (SCALER MAIN / OSD)

  44. Factory Data per each Mode 6. ASI500 Ⅱ (SCALER PIP) 8. CXA2151HD (COMPONENT MUX)

  45. Factory Data per each Mode 7. DNIe (Picture Enhancer)

  46. Factory Data per each Mode 9. AD 9883 (AD Converter) 10. Logic (PDP Driver)

  47. Factory Data per each Mode 11. TP LOG-ASI : Test Pattern LOGIC/SCALER 12. Option

  48. Signal Waveform at AV(Audio & Visual) BoardInput Signal : 8-Color Bar

  49. Signal Waveform at AV(Audio & Visual) BoardInput Signal : 8-Color Bar * Dimensions in mm

  50. Signal Waveform at AV(Audio & Visual) BoardInput Signal : 8-Color Bar

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