erm based full ml reuse methodology l.
Download
Skip this Video
Loading SlideShow in 5 Seconds..
eRM based, Full ML reuse methodology PowerPoint Presentation
Download Presentation
eRM based, Full ML reuse methodology

Loading in 2 Seconds...

play fullscreen
1 / 10

eRM based, Full ML reuse methodology - PowerPoint PPT Presentation


  • 138 Views
  • Uploaded on

eRM based, Full ML reuse methodology. Agenda. Why eRM. What is missing ? What in it for ME ? Closing the GAP - ML reuse principles Summary and Q & A. A glimpse into eRM. Standardization (env -> agent-> …, package structure, naming conventions) Reuse rules

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

eRM based, Full ML reuse methodology


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
    Presentation Transcript
    1. eRM based, Full ML reuse methodology

    2. Agenda • Why eRM. • What is missing ? • What in it for ME ? • Closing the GAP - ML reuse principles • Summary and Q & A

    3. A glimpse into eRM • Standardization • (env -> agent-> …, package structure, naming conventions) • Reuse rules • Self Contained; tagged with subtype; extendable per subtype; Passiveness option • Sequences and Sequence drivers

    4. Standard eRM usage • Usually - reusing eVCs across different environments. • use it : • in ML environment • In CL environment

    5. What is missing ? • eRM is good for eVCs. Not sufficient for ML envs for DUTs. • eVC structure fits protocol IP. Fits Less for ML env. • ML env needs less restricted structure. • ML env needs test flow.

    6. The Question : • How to reuse a full Module Level environment to the Chip Level environment ?

    7. What in it for ME ? • Standardization : • All ML envs and CL env look and feel the same. • Time - CL env. is modular and can be brought up faster. • CL simulation – mainly integration bugs • Internals checkers and monitors save debug time • May catch bugs that were skipped in ML

    8. Closing the GAP - ML reuse principles • Standardization : • Fixed basic skeleton + test flow : ML + CL envs. • Naming conventions – top ML unit, top reusable e-file, registers names • Separating reusable and non-reusable code • reset DUT / init DUT – usually not reusable. • Apply same reuse rules : • Self Contained; tagged with subtype; • extendable per subtype. Passiveness option

    9. Example - Our SoC ARM subchip ARM eVC S S S S M M M PCM eVC OCP eVC Regs pkg vr_ad DMA PCMI Main OCP Interconnect UART RAM Regs. Bridge SDIO SDIO eVC UART eVC

    10. Summary • Cadence needs to work on such methodologies further. (SVM ?!) • Meanwhile - Implement eRM rules for the ML env, and step from eRM forward.