ARINC 429 with a Host Processor on an FPGA. 2005 MAPLD International Conference September 2005 Paper #236 Ian Land Ryan Mohan. Introduction. Trends
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2005 MAPLD International Conference
RX Registers: 0 – Data Register TX Registers: 0 – Data Register
1 – Control Register 1 – Control Register
2 – Status Register 2 – Status Register
3 – Label Memory 3 – Unused
External Special Function Register Interface
Note: The above description is for a 16-Bit read/write. 32-Bit ARINC 429 data operations require two read/write operations with the appropriate CPU address and data.
During 8-Bit operations (on the 429 control/status registers, and label memory) only one of either UDS or LDS will be asserted at a time.