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LCSL Logic Circuit Simulation Language

LCSL Logic Circuit Simulation Language. Bogdan Caprita Julian Maller Sachin Nene Chaue Shen. Verilog. Hardware design language (HDL) Introduced in 1985 Main HDL along with VHDL Implement VLSI Circuits Design simulation. Fundamentals. Based on Confluence language More abstraction

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LCSL Logic Circuit Simulation Language

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  1. LCSLLogic Circuit Simulation Language Bogdan Caprita Julian Maller Sachin Nene Chaue Shen

  2. Verilog Hardware design language (HDL) Introduced in 1985 Main HDL along with VHDL Implement VLSI Circuits Design simulation

  3. Fundamentals Based on Confluence language More abstraction Functional Language Writes comparable Verilog code

  4. Why use LCSL over Verilog? -Less verbose -Easier to understand -Recursion!

  5. Implementation Design circuit(s) in LCSL Use Verilog code for simulation, synthesis

  6. LCSL is simpler Xor <- comp +A +B -X X <- A '^' B end Sys <- {Xor} {VectorInput, "In1" 1 4, Sys.A} {VectorInput, "In2" 2 4, Sys.B} {VectorOutput, "Out" 3 Sys.X} {Set, "BuildName" "Xor"}

  7. Verilog Counterpart module OneBitXor (In1_i, In2_i, Out_o); input [3:0] In1_i; input [3:0] In2_i; output [3:0] Out_o; wire [3:0] n1; assign n1 = In1_i ^ In2_i; assign Out_o = n1; endmodule

  8. Back to example Xor <- comp +A +B -X X <- A '^' B end Sys <- {Xor} {VectorInput, "In1" 1 4, Sys.A} {VectorInput, "In2" 2 4, Sys.B} {VectorOutput, "Out" 3 Sys.X} {Set, "BuildName" "OneBitXor"}

  9. Circuit implemented

  10. Functional Programming • Lambda functions • Beta reductions • “Variables” • Recursion • Evaluation λ

  11. Another example Xor <- comp +A +B -X X <- A '^' B end BusXor <- comp +A +B -X if width A == 0 X <- '' else {Xor, 'lsb' A 'lsb' B, BitX} {BusXor, 'msbs' A 'msbs' B, SubX} X <- SubX '++' BitX end end

  12. Another example (Cont’d) Sys <- {BusXor} {VectorInput, "In1" 1 4, Sys.A} {VectorInput, "In2" 2 4, Sys.B} {VectorOutput, "Out" 3 Sys.X} {Set, "BuildName" "NBitXor"}

  13. Circuit implemented

  14. module NBitXor (In1_i, In2_i, Out_o); input [3:0] In1_i; input [3:0] In2_i; output [3:0] Out_o; wire [3:0] n1; NBitXor_1 s1 (In1_i, In2_i, n1); assign Out_o = n1; endmodule module NBitXor_1 (i1, i2, o1); input [3:0] i1; input [3:0] i2; output [3:0] o1; wire n1; wire [2:0] n2; wire n3; wire [1:0] n4 wire n5; wire n6; wire n7; wire n8; wire n9; wire [2:0] n10; wire n11; wire n12; wire [1:0] n13; wire n14; wire n15; wire n16; And the Verilog for it

  15. wire n17; wire n18; wire [1:0] n19; wire [2:0] n20; wire [3:0] n21; assign n1 = i1[0]; assign n2 = {i1[3], i1[2], i1[1]}; assign n3 = n2[0]; assign n4 = {n2[2], n2[1]}; assign n5 = n4[0]; assign n6 = n4[1]; assign n7 = n6; assign n8 = i2[0]; assign n9 = n1 ^ n8; assign n10 = {i2[3], i2[2], i2[1]}; assign n11 = n10[0]; assign n12 = n3 ^ n11; assign n13 = {n10[2], n10[1]}; assign n14 = n13[0]; assign n15 = n5 ^ n14; assign n16 = n13[1]; assign n17 = n16; assign n18 = n7 ^ n17; assign n19 = {n18, n15}; assign n20 = {n19, n12}; assign n21 = {n20, n9}; assign o1 = n21; endmodule And the Verilog for it (Cont’d)

  16. Lessons learned • Separation of tasks more efficient • Managing/organizing code • Intermediate deadlines • Teamwork/Communication

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