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FRC/BC Schedule

FRC/BC Schedule. Current Status. Received prototype (bare) FRC & BC boards on 08-Mar-01 Populating FRC in steps: at each step test functionality of components Power ok Clock distrib ok Resets ok PCI FPGAs ~done TRDF,SCLF,BM FPGAs soon PCI Tests

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FRC/BC Schedule

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  1. FRC/BC Schedule STT Meeting: 30-Mar-01

  2. Current Status • Received prototype (bare) FRC & BC boards on 08-Mar-01 • Populating FRC in steps: • at each step test functionality of components • Power ok • Clock distrib ok • Resets ok • PCI FPGAs ~done • TRDF,SCLF,BM FPGAs soon • PCI Tests • modify BU’s PCI device driver to work with FRC • currently can read and write to configuration and memory space • single write mode • BC Assembly/Testing • need to build another interface board • (to interface to the interface board we just bought) STT Meeting: 30-Mar-01

  3. FRC/BC Costs Minimal Changes from Oct-00 • FRC: use 2 10K30’s instead of all 10K50’s • BC: DPRAM went from $52 to $91 / chip Total Includes • all BCs for everyone Total Does not Include • CPUs (paid for by FSU + French) • VTMs (paid for by BU) • Motherboard, SCL mezz, Link Tx’s • estimate for FRC/BC fab/assemb not final board costs updated: 03-Apr-01 STT Meeting: 30-Mar-01

  4. Cost Details FRC BC STT Meeting: 30-Mar-01

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