12/8/2009 Iowa State University EE491 - Senior Design I - PowerPoint PPT Presentation

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12/8/2009 Iowa State University EE491 - Senior Design I

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  1. 12/8/2009 Iowa State University EE491 - Senior Design I Semester design review A TEST VEHICLE FOR RESEARCH ON THERMAL MANAGEMENT FOR INTEGRATED CIRCUITSKarl Peterson , Emmanuel Owusu, and Joshua Ellis

  2. Our project is special… • International collaboration • Product conceptualization & specification in addition to design • Integrated circuit (IC) rather than system design • Research-orientated objectives

  3. Problem Statement • Design an integrated circuit (IC) for testing activities related to Iowa State University research activities in the area of thermal measurement and management for high-performance chips • Research in this area is being conducted by Dr. Randy Geiger and Dr. Degang Chen and members of their research group

  4. Problem Statement • Experimental activities related to this research have not been specifically planned • Part of our job has been to anticipate the type of tests for which the IC might be used • Flexibility and configurability are key features of the solution we have proposed • In preparation for the design, we imagined possible tests scenarios in detail and discussed them with the research team

  5. Types of IC testing activities • Evaluation of existing or novel analog temperature sensing circuits • Study of failure mechanisms affecting the long-term reliability of high-performance chips • Development of dynamic thermal management strategies taking advantage of the products of items (1) and (2)

  6. Solution approach • Flexibility can be achieved by realizing complex testing functionality on a programmable external controller • The IC itself allows test measurements to be taken and experimental conditions to be set while the controller manages these operations according to the specific test being conducted

  7. Top-level block diagram

  8. Analog test unit - subcircuits

  9. Digital functionality

  10. Design approach • ‘Divide-and-conquer’ • Top-down design methodology • Levels of design • Behavioral (Verilog, Verilog-A) • Transistor level (schematic) • Layout (mask description) • All descriptions (and documentation) are organized in Cadence design environment • Shared library

  11. Schedule • Based around January 20th submission deadline for MOSIS educational program • Very aggressive!

  12. Resources • Design & fabrication are separated in modern integrated circuit operations • Design itself is really a software task, resources include: • Software tools (Cadence front-to-back tool-set, ModelSim, etc.) • Engineering labor

  13. Table 7 - Labor costs for team members (September 2009 - April 2010) Resources - labour

  14. Risks & risk mitigation • Aggressive schedule, tight deadline • Risk of not meeting deadline • In this case, our product cannot be used for research or its use may be delayed • Near-impossibility of modification after fabrication • Statistical variations in the fabrication process • Oversights in verification

  15. Thank you! • Any questions? • Details about sub-blocks?

  16. BACKUP SLIDES

  17. CMOS Temperature sensors • Research centers around compact, low power designs • Most temperature sensors in this category are based off of a view basic architectures • Many details of their performance and operation on not well understood!

  18. ADC – Sigma-delta modulator

  19. Test interconnect

  20. Current DAC – Basic architecture