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Jet algorithm and jet FPGA

Jet algorithm and jet FPGA. by Attila Hidvégi. Content. Status of the jet algorithm Status of the jet FPGA for JEM 1.0 Tests with the jet FPGA from Stockholm Jet merging on CMM Summary Outlook. 8 x 3 bit normal. Parity. 8 x 2 bit normal. 4 x 2 bit FCAL. Parity.

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Jet algorithm and jet FPGA

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  1. Jet algorithm and jet FPGA by Attila Hidvégi

  2. Content • Status of the jet algorithm • Status of the jet FPGA for JEM 1.0 • Tests with the jet FPGA from Stockholm • Jet merging on CMM • Summary • Outlook

  3. 8 x 3 bit normal Parity 8 x 2 bit normal 4 x 2 bit FCAL Parity Status of the jet algorithm • FCAL handling is now added. • Uses 8 FCAL and 8 normal thresholds. If a cluster contains an FCAL element the FCAL thresholds are applied to that cluster. • The current jet multiplicity format is: • RoI data contain all threshold passes. • Only the two clock cycle version is used from now on. • Needs to be tested for both functionally and timing, since this is a new FPGA.

  4. Status of the new jet FPGA • Firmware is as complete as it can be for the moment. • Synthesizes a lot more smoothly. • What else needs to be done: • Test all functionally. • Create a bus where RTDP will be sent to the main FPGA. • Update default settings as needed. • Add some flashing LEDs. • Some new ideas will always show up… • Tests at RAL show some problems. Some can be explained by the wrong configuration being downloaded, others not. • Tests at Mainz show no problems at all.

  5. Tests of the Jet FPGA from Stockholm • Input values are arriving at the Jet FPGAon the wrong clock phase, due to a latency change in the input FPGA. • Input mapping is wrong. Seems to be flipped in both directions from each input FPGA. • The other features that we were able to test seem to function properly. My conclusion is therefore that the jet FPGA is working as it is supposed to.

  6. Jet Merging (Sam) • New Jet CMM firmware being written: • Separate handling of FCAL jets • Jet-Et calculation from central and FCAL jets • New readout format • More complex format than cluster merger, but Sam received good advice/support from Ian Brawn • Status: design is basically complete, but… • Code still needs some clean-up and debugging • Make sure all real-time data paths are synchronized • Should have testable firmware by beginning of August

  7. Summary • Jet FPGA firmware: • The new jet FPGA is finished. • No tests of the jet algorithm done yet. • Observed problems are well understood and will take very little time to correct. • Jet CMM firmware • New design nearly complete • Ready for testing by August

  8. Outlook • All functionality of the jet FPGA needs to be tested. • Test the functionality and timing of the jet algorithm. This will require more software programming. • Resolve any new problems that emerge. • Need to discuss schedules with Mainz, RAL

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