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Digital Electronics Tutorial: Sequential Logic Solutions

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## Digital Electronics Tutorial: Sequential Logic Solutions

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**Digital ElectronicsTutorial: Sequential Logic**Solutions ELEC1041 – Tut Sequential 1**Problem #1**In lecture, we presented an R-S latch based on cross-coupled NOR gates. It is also possible to construct an R’-S’ latch using cross-coupled NAND gates. (a)Draw the R’-S’ latch, labeling the R’ and S’ inputs and the Q and Q’ outputs. (b)Show the timing behavior across the four configurations of R’ and S’. Indicate on your timing diagram the behavior in entering and leaving the forbidden state when R’ = S’ = 0. (c)Draw the state diagram that shows the complete input/output and state transition behavior of the R’-S’ latch. (d)What is the characteristic equation of the R’-S’ latch. (e)Draw a simple schematic for a gated R-S latch with an extra enable input, using NAND gates only. ELEC1041 – Tut Sequential 2**S**Q Q R Problem #1 Solution (1/5) (a)Draw the R-S latch, labeling the R and S inputs and the Q and Q outputs. ELEC1041 – Tut Sequential 3**Race**Hold Hold Reset Reset Forbidden Forbidden Set Set S Q Q R Problem #1 Solution (2/5) (b)Show the timing behavior across the four configurations of R and S. Indicate on your timing diagram the behavior in entering and leaving the forbidden state when R=S=0. S R Q Q ELEC1041 – Tut Sequential 4**SR=01**SR=11 SR=10 SR=11 SR=01 SR=10 Q Q0 1 Q Q1 0 SR=10 SR=01 SR=00 Q Q1 1 SR=00 SR=00 SR=00 SR=11 S'R'=11 SR=10 SR=01 possible oscillationbetween states 00 and 11 Q Q0 0 Problem #1 Solution (3/5) (c)Draw the state diagram that shows the complete input/output and state transition behavior of the R’-S’ latch. ELEC1041 – Tut Sequential 5**S R Q(t) Q(t+)1 1 0 01 1 1 11 0 0 01 0 1 00 1 0 10 1 1 10 0 0 X0 0 1 X**S R Q(t) Q(t+)1 1 0 01 1 1 11 0 0 01 0 1 00 1 0 10 1 1 10 0 0 X0 0 1 X hold S reset X 1 X 1 0 0 1 0 set Q(t) R not allowed S Q Q R Problem #1 Solution (4/5) (d)What is the characteristic equation of the R-S latch. Break feedback path Q(t) Q(t+) R S characteristic equation Q(t+) = S + R Q(t) ELEC1041 – Tut Sequential 6**S**Enable R Q Q S Q Q R Problem #1 Solution (5/5) (e)Draw a simple schematic for a gated R-S latch with an extra enable input, using NAND gates only. Control when R and S inputs matter The slightest glitch on R or S while enable is high could cause change in value stored ELEC1041 – Tut Sequential 7**Problem #2**Consider a D-type storage element implemented in five different ways: (a) D-latch (i.e., D wired to the S-input and D’ wired to the R-input of an R-S latch); (b) Clock Enabled D-latch; (c) Master-Slave Clock Enabled D-Flip-flop; (d) Positive Edge-triggered Flip-flop; (e) Negative Edge-triggered Flip-flop; Complete the following timing charts indicating the behavior of these alternative storage elements. You can ignore set-up and hold time limitations (assume all constraints are meant): ELEC1041 – Tut Sequential 8**Problem #2 Solution**• (1) output from D-latch changes as D changes regardless of the clock. • (2) output from clocked D-latch changes as D does only when the clock is high. • (3) output from D M/S FF are the samples taken from the input at the falling edge of the clock. • (4) output from positive edge FF changes relative to D at the rising edge of the clock. • (5) output form negative edge FF are the samples taken from the input at the falling edge of the clock (same as part 3). ELEC1041 – Tut Sequential 9**Problem #3**• Complete the timing diagram for this circuit. ELEC1041 – Tut Sequential 10**Problem #3 Solution**• Complete the timing diagram for this circuit. Toggles when T = 1 at the rising edge of the clock ELEC1041 – Tut Sequential 11**Problem #4**• Design a 4 bit counter that counts through the sequence 0111, 1000, 1001, 1010, 1011, 1100, 1101 ELEC1041 – Tut Sequential 12**Problem #4 Solution**• Design a 4 bit counter that counts through the sequence 0111, 1000, 1001, 1010, 1011, 1100, 1101 "1" "0"“1"“1"“1" EN DCBA LOAD CLK CLR RCO QDQCQBQA ELEC1041 – Tut Sequential 13**Problem #5**• You as a designer at XILION Micro Devices, have been asked to redesign part of your system to run at double the clock frequency. However, to maintain the compatibility with other parts of the system you like to keep the same clock frequency. What would you do to impress your Boss? • Discuss all timing constraint in your design ELEC1041 – Tut Sequential 14**B**CLOCK CLOCK B CLK Problem #5 Solution • One way is to double of the clock frequency locally, or put it in another way make your flip flop to be both positive and negative edged triggered. Flip flop sample on both edges Conditions: Clk period 1. High Width of “CLK” should be larger than that required by the Flip Flop This can be controlled by the number of invertors (odd) before the XNOR gate. 2. Period of “CLK” should be larger than the (set up time + propagation Delay) of flip flop. ELEC1041 – Tut Sequential 15**Problem #6**• Complete the count sequence table for the following shift register circuit. Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 0 0 0 0 0 0 0 0 ELEC1041 – Tut Sequential 16**Problem #6 Solution**• Complete the count sequence table for the following shift register circuit. Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 0 1 1 1 0 1 1 0 0 0 1 1 1 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 1 1 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 1 0 0 1 1 0 0 1 0 1 0 ELEC1041 – Tut Sequential 17**Problem #7**Consider the counter x74_163 from the xilinx library. Complete the timing diagram Below: (Note: LOAD and CLR are active low. P & T should be high to enable the counter P 163 T RCO CLK D QD C QC B QB QA A LOAD CLR ELEC1041 – Tut Sequential 18**Problem #7 Solution**Indicates Undefined Clear Load P & T should be High to enable count ELEC1041 – Tut Sequential 19**Problem #8**Design the logic for a 3-bit counter that follows the following sequence: 000, 111, 001, 110, 010, 101, 011, 100, 000 and repeats. Design the counter so when Reset is asserted, the counter enters the state 000. ELEC1041 – Tut Sequential 20**Problem #8 Solution (1/2)**Design the logic for a 3-bit counter that follows the following sequence: 000, 111, 001, 110, 010, 101, 011, 100, 000 and repeats. Design the counter so when Reset is asserted, the counter enters the state 000. ELEC1041 – Tut Sequential 21**Problem #8 Solution (2/2)**ELEC1041 – Tut Sequential 22**Problem #9**Design the logic for a 3-bit counter that follows the following sequence: 001, 010, 100, 101, 110, 001, and repeat. Design the counter so that it is self-starting, i.e., whatever state it comes up in, it will eventually get into the sequence as shown above. ELEC1041 – Tut Sequential 23**111**001 010 100 101 110 000 011 + Q2 = Q2 Q1 + Q2Q1 + Q0 = Q1 Q0 + Q2Q1 + Q1 = Q1 Q0 Problem #9 Solution + + + ELEC1041 – Tut Sequential 24**Problem #10**Consider 3 bit Johnson Counter below. Derive it state transition table and diagrams ELEC1041 – Tut Sequential 25**Problem #10 Solution**+ + + Q2Q1Q0 000 111 Q2Q1Q0 0 0 0 0 0 1 0 0 1 0 1 1 0 1 0 1 0 0 0 1 1 1 1 0 1 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 0 1 1 1 1 1 0 001 110 010 101 011 100 ELEC1041 – Tut Sequential 26**Problem #11**ELEC1041 – Tut Sequential 27**Problem #11 Solution (1/2)**ELEC1041 – Tut Sequential 28**q0**q0 q0 1 0 0 1 0 0 0 1 0 1 1 0 0 x 1 x 0 x 1 x 1 x 1 x X X X q1 q1 q1 Z D0 D1 Problem #11 Solution (2/2) ELEC1041 – Tut Sequential 29**Problem #12**ELEC1041 – Tut Sequential 30**Problem #12 Solution (1/3)**ELEC1041 – Tut Sequential 31**Problem #12 Solution (2/3)**ELEC1041 – Tut Sequential 32**q2**q2 D1 D2 0 0 x 1 1 0 x x 1 1 x x 0 0 x 0 0 0 x 0 0 0 x x 0 0 x x 0 1 x 0 q0 q0 X X q1 q1 q2 q2 Z D0 0 1 x 0 1 1 x x 1 0 x x 0 1 x 0 0 1 x 0 0 1 x x 1 0 x x 1 0 x 0 q0 q0 X X q1 q1 Problem #12 Solution (3/3) ELEC1041 – Tut Sequential 33**Problem #13**Finite String Pattern Recognizer A finite string recognizer has one input (X) and one output (Z). The output is asserted whenever the input sequence …010… has been observed, as long as the sequence 100 has never been seen. Step 1. Understanding the problem statement Sample input/output behavior: X: 00101010010… Z: 00010101000… X: 11011010010… Z: 00000001000… ELEC1041 – Tut Sequential 34**Reset**S0 [0] 1 0 S4 S1 [0] [0] 0 1 S2 S5 [0] [0] 0 0 0,1 S3 S6 Loops in State Outputs 1 [1] [0] Problem #13 Solution (1/5) Step 2. Draw State Diagrams/ASM Charts for the strings that must be recognized. I.e., 010 and 100. Moore State Diagram Reset signal places FSM in S0 ELEC1041 – Tut Sequential 35**Reset**S0 [0] 1 0 S4 S1 [0] [0] 0 1 S2 S5 [0] [0] 0 1 0 0,1 0 S3 S6 [1] [0] Problem #13 Solution (2/5) Exit conditions from state S3: have recognized …010 if next input is 0 then have …0100! if next input is 1 then have …0101 = …01 (state S2) ELEC1041 – Tut Sequential 36**Reset**S0 [0] 1 0 0 1 S4 S1 [0] [0] 0 1 S2 S5 [0] [0] 0 1 0 0,1 0 S3 S6 [1] [0] Problem #13 Solution (3/5) Exit conditions from S1: recognizes strings of form …0 (no 1 seen) loop back to S1 if input is 0 Exit conditions from S4: recognizes strings of form …1 (no 0 seen) loop back to S4 if input is 1 ELEC1041 – Tut Sequential 37**1**0 0 1 0 1 1 1 0 1 0 0,1 0 Problem #13 Solution (4/5) S2, S5 with incomplete transitions S2 = …01; If next input is 1, then string could be prefix of (01)1(00) S4 handles just this case! S5 = …10; If next input is 1, then string could be prefix of (10)1(0) S2 handles just this case! Reset S0 [0] S4 S1 [0] [0] Final State Diagram S2 S5 [0] [0] S3 S6 [1] [0] ELEC1041 – Tut Sequential 38**Problem #13 Solution (5/5)**Finite String Recognizer Review of Process: • Write down sample inputs and outputs to understand specification • Write down sequences of states and transitions for the sequences to be recognized • Add missing transitions; reuse states as much as possible • Verify I/O behavior of your state diagram to insure it functions like the specification ELEC1041 – Tut Sequential 39**Problem #14**Finite String Pattern Recognizer A finite string recognizer has one input (X) and two output (Z1 & Z2). The output Z1 is asserted whenever the input sequence …010… has been observed, as long as the sequence 100 has never been seen. The output Z2 is asserted whenever the input sequence …100… has been observed Note that once Z2 = 1 has occurred, Z1 = 1 can never occur, but never vice versa Step 1. Understanding the problem statement Sample input/output behavior: X : 0010101001000… Z1: 0001010100000… Z2: 0000000010010… X : 110110100100… Z1: 000000010000… Z2: 000000001001… ELEC1041 – Tut Sequential 40**Reset**S0 [00] S4 1 S1 0 [00] [00] 0 1 S2 S5 [00] [00] 0 0 S3 S6 Output Z2= 1 [Z1=1] [Z2=1] Output Z1= 1 Problem #14 Solution (1/8) Step 2. Draw State Diagrams/ASM Charts for the strings that must be recognized. I.e., 010 and 100. Moore State Diagram Reset signal places FSM in S0 ELEC1041 – Tut Sequential 41**Reset**S0 [00] 1 0 S4 S1 [00] [00] 0 1 S2 S5 [00] [00] 0 1 0 S3 S6 0 [Z1=1] [Z2=1] Problem #14 Solution (2/8) Exit conditions from state S3: have recognized …010 if next input is 0 then have …0100! if next input is 1 then have …0101 = …01 (state S2) ELEC1041 – Tut Sequential 42**Reset**S0 [00] 1 0 0 1 S4 S1 [00] [00] 0 1 S2 S5 [00] [00] 0 1 0 0 S3 S6 [Z1=1] [Z2=1] Problem #14 Solution (3/8) Exit conditions from S1: recognizes strings of form …0 (no 1 seen) loop back to S1 if input is 0 Exit conditions from S4: recognizes strings of form …1 (no 0 seen) loop back to S4 if input is 1 ELEC1041 – Tut Sequential 43**1**0 0 1 0 1 1 1 0 1 0 0 Problem #14 Solution (4/8) S2, S5 with incomplete transitions S2 = …01; If next input is 1, then string could be prefix of (01)1(00) S4 handles just this case! S5 = …10; If next input is 1, then string could be prefix of (10)1(0) S2 handles just this case! Reset S0 [00] S4 S1 [00] [00] S2 S5 [00] [00] S3 S6 [Z1=1] [Z2=1] ELEC1041 – Tut Sequential 44**1**0 0 1 0 1 1 1 0 1 0 0 Problem #14 Solution (5/8) S6 = …100; If next input is 1, then string could be prefix of (100)1(00) S4 handles just this case! BUT IS IT? Remember S3 should never be entered again, so S5 should be avoided Reset S0 [00] S4 S1 [00] [00] Final State Diagram S2 S5 1 [00] [00] S3 S6 [Z1=1] [Z2=1] ELEC1041 – Tut Sequential 45**1**0 0 1 0 1 1 1 0 1 0 S8 S7 [00] [00] 0 Problem #14 Solution (6/8) S6 = …100; If next input is 1, then string could be prefix of (100)1(00) Draw additional states for the string that must be recognized after S6 has been entered i.e. 100. Reset S0 [00] S4 S1 [00] [00] S2 S5 [00] [00] 0 0 1 S3 S6 [Z1=1] [Z2=1] ELEC1041 – Tut Sequential 46**1**0 0 1 0 1 1 1 0 1 0 S7 S8 S9 [00] [00] [00] 0 Problem #14 Solution (7/8) S6 = …100; If next input is 1, then string could be prefix of (100)1(00) Draw additional states for the string that must be recognized after S6 has been entered i.e. 100. Reset S0 [00] S4 S1 [00] [00] S2 S5 [00] [00] 0 0 1 S3 S6 [Z1=1] [Z2=1] 0 ELEC1041 – Tut Sequential 47**1**0 0 1 0 1 1 1 1 1 0 1 0 S7 S8 S9 1 [00] [00] [00] 0 0 Problem #14 Solution (8/8) S6 = …100; If next input is 1, then string could be prefix of (100)1(00) Draw additional states for the string that must be recognized after S6 has been entered i.e. 100. Reset S0 [00] S4 S1 [00] [00] S2 S5 [00] [00] 0 0 1 S3 S6 [Z1=1] [Z2=1] 0 ELEC1041 – Tut Sequential 48**Problem #15**N + 2 converter A sequential network has one input X and two outputs S and V. X represent a four bit binary number N, which is input least significant bit first. S represents a four bit binary number equal to N + 2, which is output least significant bit first. At the time the fourth input is sampled, V = 1, in N + 2 is too large to be represented by four bits; otherwise V = 0. Derive a Mealy state graph and table with a minimum number of states ELEC1041 – Tut Sequential 49**Problem #15 Solution (1/3)**X S V N3N2N1N0 S (N) (N +2) 0 0000 0010 0 1 0001 0011 0 2 0010 0100 0 3 0011 0101 0 4 0100 0110 0 5 0101 0111 0 6 0110 1000 0 7 0111 1001 0 8 1000 1010 0 9 1001 1011 0 10 1010 1100 0 11 1011 1101 0 12 1100 1110 0 13 1101 1111 0 14 1110 0000 1 15 1111 0001 1 FSM X V Example: N +2 Serial Converter Assume numbers are +ve (0N15) Conversion Process Bits are presented in bit serial fashion starting with the least significant bit Single input X, Two output S, V ELEC1041 – Tut Sequential 50