RISC Architecture and Pipelining

RISC Architecture and Pipelining Joel C. Frank CS147 Spring 2005

Overview • RISC • Pipeline Cycle • Problems with pipelining • Dynamic Branch Prediction • Branch Correlation • Pipelining Optimization

RISC • Reduced Instruction Set Computer • Minimum set of instructions • One instruction per clock cycle • All instructions are the same length

RISC Pipelines • Fetch Instructions from memory • Read registers and decode the instruction • Execute the instruction or calculate an address • Access an operand in data memory • Write the result into a register

Pipeline Problems • Is not faster in all cases • Must be able to: • Break the process into independent stages • Each stage must take the same amount of time • The overhead to move data from one stage to another must be insignificant

Pipeline Problems - Overhead • Setup Time • Time required to restart a pipeline • Pass a control token through the pipeline to restart each stage • Flush Time • Performed prior to shutting down the pipeline • Most pipelines have significant termination time • Stalls

Pipeline Problems - Stalls • RISC processors typically operate at more than 1 cycle / instruction • Data Dependency – an instruction depends on the outcome of a previous instruction add $r3, $r2, $r1 add $r5, $r4, $r3 Stall Creates ‘Bubbles’ in the pipeline

MIPS Solution to Stalling • Code Reordering add $r3, $r2, $r1 add $r5, $r4, $r3 add $r8, $r7, $r6 • Branch Prediction • Static • Dynamic Loop : add $r3, $r2, $r1 sub $r6, $r5, $r4 beq $r3, $r6, Loop

Dynamic Branch Prediction • Branch History Table (BHT) • Lower bits of branch address index table • 1-bit values • Says whether or not branch taken last time • If branch was taken last time, then take again • Initially, bits are set to predict that all branches are taken • 2-Bit predictor scheme – most common • Changes prediction only if wrong 2x for a given branch • Accuracy is a function of the number of loops • More loops = More accurate • Accuracy Range: 1-18% gcc ~12%

Branch Correlation if (aa == 2) aa = 0; if (bb == 2) bb = 0; if (aa != bb) cc = 4; • Recent branches’ behavior affects the prediction of the current branch • Uses last m branches to choose between 2m predictors 4096 Entries 2-bit BHT Unlimited Entries 2-bit BHT 1024 Entries (2,2) BHT gcc

Pipeline Optimization • Superpipelining • Divides the pipeline into more steps • Typically breaks the fetch and access steps into two or more steps • Allows for ‘forked’ pipelines • Dynamic Pipelining • 3 main units • In / Out of order • Can schedule around stalls

Summary • RISC • Pipeline Cycle • Problems with pipelining • Overhead • Stalls • Dynamic Branch Prediction • Branch Correlation • Pipelining Optimization

References • Essentials of Computer Architecture • http://cse.stanford.edu/class/sophomore-college/projects-00/risc/pipelining/ • http://www.cs.berkeley.edu/~randy/Courses/CS252.S96/Lecture12.pdf • http://www.hardwarecentral.com/hardwarecentral/tutorials/2427/1/ • http://arstechnica.com/articles/paedia/cpu/pipelining-1.ars/1

RISC Architecture and Pipelining