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时序电路设计描述. 时序电路的总体结构. …. OUTPUT. INPUT. …. Combinational Logic Circuit. DataPath / Control Path. …. …. …. Storage element. …. 时序电路设计描述. FSM. …. …. 寄 存 器 文 件. 寄 存 器 文 件. 寄 存 器 文 件. DataPath. DataPath. 时序电路设计描述. 时序电路设计描述. 描述内容: 组合逻辑通路; 数据通路结构; 控制通路结构;

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slide2

时序电路的总体结构

OUTPUT

INPUT

Combinational Logic Circuit

DataPath / Control Path

Storage element

时序电路设计描述
slide3

FSM

DataPath

DataPath

时序电路设计描述
slide4
时序电路设计描述

描述内容:

  • 组合逻辑通路;
  • 数据通路结构;
  • 控制通路结构;
  • 数据传输方式/存储元件(寄存器文件)操作;
  • 时钟控制方式;
  • 存储元件的置/复位方式;
  • 时钟系统结构
slide5
时序电路设计描述

基本存储元件

  • Latch
  • D_FlipFlop
slide6

D

D

Q

Q

Latch

Latch

Q_Bar

Q_Bar

En

En

时序电路设计描述

注意:组合逻辑通路描述中,若分支描述结构中的描述不满时,易出现不必要的Latch,导致综合结果错误!!!

always @( En or D )

if ( En ) { Q, Q_bar } = { D, ~D};

always @(En or D or Reset)

if ( ~Reset) {Q, Q_bar} = 2’b01;

else if ( En ) {Q,Q_bar} = { D, ~D};

Reset

slide7

{Q, Q_bar } = 2’b01;

{Q, Q_bar} = { D, ~D};

时序电路设计描述

always @(posedge clk) Q = D;

always @(posedge clk) {Q , Q_bar} = { D, ~D};

always @(posedge clk)

if (Reset) Q = 1’b0;

else Q = D ;

slide8
时序电路设计描述

lways @(posedge clk or negedge Reset)

if (~Reset) Q = 1’b0;

else Q = D;

always @( posedge clk or negedge Reset

or posedge Set)

if (~Reset & Set) Q = 1’bx;

else if (~Reset) Q = 1’b0;

else if (Set) Q= 1’b1;

else Q = D;

slide9

D

Q

Clk

Reset

时序电路设计描述

always @(posedge clk or negedge Reset )

if ( ~Reset ) Q = 1’b0 ;

else Q = D ;

always @( posedge clk)

Q = D;

always @( negedge Reset )

Q = 1’b0;

posedge clk 、negedge Reset

同时出现,Q不定或错误;

posedge clk 、negedge Reset

不同时出现,模拟正确

综合不出带复位的触发器

slide10
时序电路设计描述

always @(posedge clk {or negedge Reset } ) Stm描述形式的理解

  • 正确区分Stm描述体中各个赋值语句执行的次序;
  • 特别注意Stm描述体中的非阻塞赋值语句(NonBlocking Stms);
  • 特别注意Stm描述体中Blocking 和NonBlocking赋值语句的执行顺序
slide11
时序电路设计描述

并发执行

产生4组触发器

只对变量d寄存

只产生一组触发器

slide13
时序电路设计描述

……

reg A,B,C,D,E;

reg M,N, Y;

always @( C or D) N= C | D;

always @(posedge Clk)

begin

M = !(A & B);

Y = ! (M | N | E );

end

……..

……

reg A,B,C,D,E;

reg M,N, Y;

always @( C or D) N= C | D;

always @(posedge Clk)

begin

M <= !(A & B);

Y = ! (M | N | E );

end

……..

Y = ! (M |N | E);

M = ! (A & B) ;

Y <= ( M | N | E ) ;

slide14

尽量避免采用的描述形式

建议采用的描述形式

时序电路设计描述

……

reg [16:0] A, B , C, E;

reg [17:0] F;

always @(posedge clk )

begin

C = A + B;

if ( C == 16’hFF )

E = A – B;

else E= C;

F = E *2;

end

…….

……

reg [16:0] A, B , C, E;

reg [17:0] F;

always (A or B)

begin

C = A + B;

if ( C == 16’hFF )

E = A – B;

else E= C;

end

always @(posedge clk)

F = E <<1;

…….

只对F产生寄存

slide15

并发执行

易导致模拟错误

时序电路设计描述

…..

reg [7:0] A,B,C,D,F,G;

reg F;

always @(posedge clk)

begin

D = A + B;

F = D & C;

Parity = ^ F;

end

always @(posedge clk)

begin

if (Parity) G = F;

else G = D;

end

…….

G可能取什么值??

slide16

存储F的值

时序电路设计描述

…..

reg [7:0] A,B,C,D,F,G;

reg F;

always @(posedge clk)

begin

D = A + B;

F = D & C;

Parity = ^ F;

if ( Parity ) G = F;

else G = D;

end

…….

…..

reg [7:0] A,B,C,D,F,G;

reg F;

always @(posedge clk)

begin

D = A + B;

F <= D & C;

Parity = ^ F;

if ( Parity ) G = F;

else G = D;

end

…….

slide17
时序电路设计描述

时序逻辑电路描述中,

  • 尽量将组合逻辑通路(函数功能)和数据传输逻辑分开,并分别加以描述;
  • 注意数据传输逻辑描述块中各个描述语句的执行次序及其对应的逻辑结构,特别是其时序结构;
  • 注意各个数据传输逻辑描述块的并行执行的特征,特别注意各种数据的相关性。
slide18
时序电路设计描述

线性反馈移位寄存器(LFSR)

结构

  • n位LFSR是由n个触发器和一个反馈回路组成。
  • 内异或结构(One-to-Many)
  • 外异或结构( Many-to-One)
slide19

x1

x2

Xn-1

xn

……

D0

D1

Dn

……

h0=1

hn=1

hn-1

h1

h2

LFSR结构

内异或结构LFSR

LSFR的位长n和参数向量

(h0,h1,…,hn)

hi=0表示触发器Di直接接收Di-1的输出

slide20

x1

x2

Xn-1

……

xn

D0

D1

Dn

……

hn-1

h1

h2

hn=1

h0=1

XOR (NXOR)

LFSR

外异或结构(Many_to_One)

slide21
LFSR

如何构造LFSR?

问题:给定LFSR的位数N、LFSR采用的总体结构、特征向量(h0,h1,…,hn),构造LFSR ?

slide22

初始化

module LFSR_N_XOR1(clk,Reset,Y);

parameter N =8;

input clk,Reset;

output [N-1:0] Y;

reg [N-1:0] Y;

reg [31:0] Harray [2:32];

wire [N-1:0] H;

integer m;

reg [N-1:0] LFSR_PS, LFSR_NS;

always @(Reset)

begin

特征存储器初始化;

end

assign H = Harray[N];

always @(posedge clk or negedge Reset)

if (~Reset) LFSR_PS =初值;

else LFSR_PS = LFSR_NS;

LFSR 寄存器序列状态转换

1

slide23

always @( LFSR_PS)

begin

计算Feedback值;

for (m=N-1; m>=1;m=m-1)

if (H[m] ==1’b1)

LFSR_NS[m] = LFSR_PS[m-1] ^ Feedback;

else LFSR_NS[m] =LFSR_PS[m-1];

LFSR_NS[0] = Feedback;

end

endmodule

LFSR码序列转换

2

Feedback的取值问题?

slide24
时序电路设计描述

时序电路设计描述包括:

  • 数据通路/控制通路描述;
  • FSM描述;
  • 数据传输描述;
  • 时钟系统描述;