1 / 24

时序电路设计描述 - PowerPoint PPT Presentation

I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.

PowerPoint Slideshow about '时序电路设计描述' - morwenna-awena

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.

- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript

时序电路设计描述

OUTPUT

INPUT

Combinational Logic Circuit

DataPath / Control Path

Storage element

FSM

DataPath

DataPath

• 组合逻辑通路；
• 数据通路结构；
• 控制通路结构；
• 数据传输方式/存储元件(寄存器文件)操作；
• 时钟控制方式；
• 存储元件的置/复位方式；
• 时钟系统结构

• Latch
• D_FlipFlop

D

D

Q

Q

Latch

Latch

Q_Bar

Q_Bar

En

En

always @( En or D )

if ( En ) { Q, Q_bar } = { D, ~D};

always @(En or D or Reset)

if ( ~Reset) {Q, Q_bar} = 2’b01;

else if ( En ) {Q,Q_bar} = { D, ~D};

Reset

{Q, Q_bar } = 2’b01;

{Q, Q_bar} = { D, ~D};

always @(posedge clk) Q = D;

always @(posedge clk) {Q , Q_bar} = { D, ~D};

always @(posedge clk)

if (Reset) Q = 1’b0;

else Q = D ;

lways @(posedge clk or negedge Reset)

if (~Reset) Q = 1’b0;

else Q = D;

always @( posedge clk or negedge Reset

or posedge Set)

if (~Reset & Set) Q = 1’bx;

else if (~Reset) Q = 1’b0;

else if (Set) Q= 1’b1;

else Q = D;

D

Q

Clk

Reset

always @(posedge clk or negedge Reset )

if ( ~Reset ) Q = 1’b0 ;

else Q = D ;

always @( posedge clk)

Q = D;

always @( negedge Reset )

Q = 1’b0;

posedge clk 、negedge Reset

posedge clk 、negedge Reset

always @(posedge clk {or negedge Reset } ) Stm描述形式的理解

• 正确区分Stm描述体中各个赋值语句执行的次序；
• 特别注意Stm描述体中的非阻塞赋值语句(NonBlocking Stms)；
• 特别注意Stm描述体中Blocking 和NonBlocking赋值语句的执行顺序

……

reg A,B,C,D,E;

reg M,N, Y;

always @( C or D) N= C | D;

always @(posedge Clk)

begin

M = !(A & B);

Y = ! (M | N | E );

end

……..

……

reg A,B,C,D,E;

reg M,N, Y;

always @( C or D) N= C | D;

always @(posedge Clk)

begin

M <= !(A & B);

Y = ! (M | N | E );

end

……..

Y = ! (M |N | E);

M = ! (A & B) ;

Y <= ( M | N | E ) ;

……

reg [16:0] A, B , C, E;

reg [17:0] F;

always @(posedge clk )

begin

C = A + B;

if ( C == 16’hFF )

E = A – B;

else E= C;

F = E *2;

end

…….

……

reg [16:0] A, B , C, E;

reg [17:0] F;

always (A or B)

begin

C = A + B;

if ( C == 16’hFF )

E = A – B;

else E= C;

end

always @(posedge clk)

F = E <<1;

…….

…..

reg [7:0] A,B,C,D,F,G;

reg F;

always @(posedge clk)

begin

D = A + B;

F = D & C;

Parity = ^ F;

end

always @(posedge clk)

begin

if (Parity) G = F;

else G = D;

end

…….

G可能取什么值？？

…..

reg [7:0] A,B,C,D,F,G;

reg F;

always @(posedge clk)

begin

D = A + B;

F = D & C;

Parity = ^ F;

if ( Parity ) G = F;

else G = D;

end

…….

…..

reg [7:0] A,B,C,D,F,G;

reg F;

always @(posedge clk)

begin

D = A + B;

F <= D & C;

Parity = ^ F;

if ( Parity ) G = F;

else G = D;

end

…….

• 尽量将组合逻辑通路（函数功能）和数据传输逻辑分开，并分别加以描述；
• 注意数据传输逻辑描述块中各个描述语句的执行次序及其对应的逻辑结构，特别是其时序结构；
• 注意各个数据传输逻辑描述块的并行执行的特征，特别注意各种数据的相关性。

• n位LFSR是由n个触发器和一个反馈回路组成。
• 内异或结构(One-to-Many)
• 外异或结构( Many-to-One)

x1

x2

Xn-1

xn

……

D0

D1

Dn

……

h0=1

hn＝1

hn-1

h1

h2

LFSR结构

LSFR的位长n和参数向量

（h0,h1,…,hn)

hi＝0表示触发器Di直接接收Di－1的输出

x1

x2

Xn-1

……

xn

D0

D1

Dn

……

hn-1

h1

h2

hn＝1

h0=1

XOR （NXOR）

LFSR

LFSR

module LFSR_N_XOR1(clk,Reset,Y);

parameter N =8;

input clk,Reset;

output [N-1:0] Y;

reg [N-1:0] Y;

reg [31:0] Harray [2:32];

wire [N-1:0] H;

integer m;

reg [N-1:0] LFSR_PS, LFSR_NS;

always @(Reset)

begin

end

assign H = Harray[N];

always @(posedge clk or negedge Reset)

if (~Reset) LFSR_PS =初值；

else LFSR_PS = LFSR_NS;

LFSR 寄存器序列状态转换

1

always @( LFSR_PS)

begin

for (m=N-1; m>=1;m=m-1)

if (H[m] ==1’b1)

LFSR_NS[m] = LFSR_PS[m-1] ^ Feedback;

else LFSR_NS[m] =LFSR_PS[m-1];

LFSR_NS[0] = Feedback;

end

endmodule

LFSR码序列转换

2

Feedback的取值问题？

• 数据通路/控制通路描述；
• FSM描述；
• 数据传输描述；
• 时钟系统描述；