1 / 61

March 2004 Modified from notes by Saeid Nooshabadi Saeid@unsw.au

COMP 3221 Microprocessors and Embedded Systems Lectures 4/5: Making Decisions in C/Assembly Language - I http://www.cse.unsw.edu.au/~cs3221. March 2004 Modified from notes by Saeid Nooshabadi Saeid@unsw.edu.au. C Decisions (Control Flow): if statements. 2 kinds of if statements in C

moriah
Download Presentation

March 2004 Modified from notes by Saeid Nooshabadi Saeid@unsw.au

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. COMP 3221 Microprocessors and Embedded Systems Lectures 4/5: Making Decisions in C/Assembly Language - Ihttp://www.cse.unsw.edu.au/~cs3221 March 2004 Modified from notes by Saeid Nooshabadi Saeid@unsw.edu.au

  2. C Decisions (Control Flow): if statements • 2 kinds of if statements in C • if (condition) statement • if (condition) statement1elsestatement2 • Following code is same as 2nd if if (condition) goto L1;statement2;goto L2;L1: statement1; L2: • Not as elegant as if-else, but same meaning

  3. ARM decision instructions (control flow) (#1/2) • Decision instruction in ARM: • cmp register1, register2 ;compare register1 with ; register2 • beq L1; branch to L1 if equal is “Branch if (registers are) equal” Same meaning as C: • if (register1==register2) goto L1 • Complementary ARM decision instruction • cmp register1, register2 • bne L1 • bne is “Branch if (registers are) not equal” Same meaning as C: if (register1!=register2) goto L1 • Called conditional branches

  4. ARM decision instructions (control flow) (#2/2) • Decision instruction in ARM: • cmp register1, #immediate ;compare register1 with ; immediate number • beq L1; branch to L1 if equal • is “Branch if (register and immediate are) equal” Same meaning as C: • if (register1==#immediate) goto L1 • Complementary ARM decision instruction • cmp register1, #immediate • bne L1 • bne is “Branch if (register and immediate are) not equal” Same meaning as C: if (register1!=#immediate) goto L1 • Called conditional branches

  5. (false) i != j (true) i == j f=g+h f=g-h i == j? Compiling C if into ARM Assembly • Compile by hand if (i == j) f=g+h; else f=g-h; Mapping f: v1, g: v2, h: v3, i: v4, j: v5 • Start with branch:cmp v4, v5 beq L-true; branch to L-True; if i==j • Follow with false partsub v1,v2,v3 ; f=g-h exit

  6. Compiling C if into ARM Assembly • Need instruction that always transfers control to skip over true part • ARM has branch: b label ; goto “label” sub v1,v2,v3 ; f=g-h b L-exit • Next is true part L-true: add v1,v2,v3; f=g+h • Followed by exit branch label L-exit:

  7. (false) i != j (true) i == j f=g+h f=g-h i == j? Compiling C if into ARM: Summary • Compile by hand if (i == j) f=g+h; else f=g-h; Mapping f: v1, g: v2, h: v3, i: v4, j: v5 cmp v4,v5 beq L-true; branch i==jsub v1,v2,v3 ; (false)b L-exit ; go to ExitL-true: add v1,v2,v3 ;(true)L-exit: • Note:Compiler supplies labels for branches not found in HLL code; often it flips the condition to branch to false part C A R M

  8. Motoring with Microprocessors • Thanks to the magic of microprocessors and embedded systems, our cars are becoming safer, more efficient, and entertaining. • The average middle-class household includes over 40 embedded processors. About half are in the garage. Cars make a great vehicle for deploying embedded processors in huge numbers. These processors provide a ready source of power, ventilation, and mounting space and sell in terrific quantities. • How many embedded processors does your car have? • If you've got a late-model luxury sedan, two or three processors might be obvious in the GPS navigation system or the automatic distance control. Yet you'd still be off by a factor of 25 or 50. The current 7-Series BMW and S-class Mercedes boast about 100 processors apiece. A relatively low-profile Volvo still has 50 to 60 baby processors on board. Even a boring low-cost econobox has a few dozen different microprocessors in it. • Your transportation appliance probably has more chips than your Internet appliance. • New cars now frequently carry 200 pounds of electronics and more than a mile of wiring. http://www.embedded.com/

  9. COMP3221 Reading Materials (Week #5) • Week #5: Steve Furber: ARM System On-Chip; 2nd Ed, Addison-Wesley, 2000, ISBN: 0-201-67519-6. We use chapters 3 and 5 • ARM Architecture Reference Manual –On CD ROM • A copy of the article by Cohen, D. “On holy wars and a plea for peace (data transmission).” Computer, vol.14, (no.10), Oct. 1981. p.48-54, is place on the class website.

  10. Loops in C/Assembly • Simple loop in C Loop: g = g + A[i]; i = i + j; if (i != h) goto Loop; • (g,h,i,j:v2,v3,v4,v5; base of A[]:v6): • 1st fetch A[i] Loop: ldr a1,[v6, v4, lsl #2] ;(v6+v4*4)=addr A[i] ;a1=A[i]

  11. Simple Loop (cont) • Add value of A[i] to g and then j to ig = g + a1 i = i + j; • (g,h,i,j:v2,v3,v4,v5): add v2,v2,a1; g = g+A[i]add v4,v4,v5; i = i + j The final instruction branches back to Loop if i != h : cmp v4,v3 bne Loop ; goto Loop ; if i!=h

  12. Loops in C/Assembly: Summary Loop: g = g + A[i]; i = i + j; if (i != h) goto Loop; • (g,h,i,j:v2,v3,v4,v5; base of A[]:v6): Loop: ldr a1,[v6, v4, lsl #2] ;(v6+v4*4)=addr A[i] ;a1=A[i] add v2,v2,a1; g = g+A[i]add v4,v4,v5; i = i + jcmp v4,v3 bne Loop ; goto Loop ; if i!=h C A R M

  13. while in C/Assembly: • Although legal C, almost never write loops with if, goto: use while, or for loops • Syntax: while(condition) statement while (save[i] == k) i = i + j; • 1st load save[i] into a scratch register (i,j,k: v4,v5,v6: base of save[]:v7): Loop: ldr a1,[v7,v4,lsl #2] ;v7+v4*4=addr of save[i] ;a1=save[i]

  14. While in C/Assembly (cont) • Loop test: exit if save[i] != k (i,j,k: v4,v5,v6: base of save[]:v7) cmp a1,v6 bne Exit ;goto Exit;if save[i]!=k • The next instruction adds j to i: add v4,v4,v5 ; i = i + j • End of loop branches back to the while test at top of loop. Add the Exit label after: b Loop ; goto LoopExit:

  15. While in C/Assembly: Summary C while (save[i]==k) i = i + j; (i,j,k: v4,v5,v6: base of save[]:v7) Loop: ldr a1,[v7,v4,lsl #2] ;v7+v4*4=addr of save[i] ;a1=save[i] cmp a1,v6 bne Exit ;goto Exit;if save[i]!=kadd v4,v4,v5 ; i = i + j b Loop ; goto LoopExit: A R M

  16. Beyond equality tests in ARM Assembly (#1/2) • So far ==, != , What about < or >? • cmp register1, register2 • blt L1 is “Branch if (register1 <register2) Same meaning as C: • if (register1<register2) go to L1 • Complementary ARM decision instruction • cmp register1, register2 • bge L1 • bge is “Branch if (register1 >= register2) ” Same meaning as C: if (register1>=register2) go to L1

  17. Beyond equality tests in ARM Assembly (#2/2) • Also • cmp register1, #immediate • blt L1 is “Branch if (register1 <#immediate) Same meaning as C: • if (register1<immediate) go to L1 • Complementary ARM decision instruction • cmp register1, #immediate • bge L1 • bge is “Branch if (register1 >= #immediate) ” Same meaning as C: if (register1>=immediate) go to L1

  18. If less_than in C/Assembly C if (g < h) { ... } cmp v1,v2; v1<v2 (g<h) blt Less ; if (g < h) b noLess ; if (g >= h) Less: ...noLess: Alternative Code cmp v1,v2; v1<v2 (g<h) bge noLess ; if (g >= h) ...; if (g < h) noLess: A R M

  19. Some Branch Conditions • b Unconditional • bal Branch Always • beq Branch Equal • bne Branch Not Equal • blt Branch Less Than • ble Branch Less Than or Equal • bgt Branch Greater Than • bge Branch Greater Than or Equal • Full Table Page 64 Steve Furber: ARM System On-Chip; 2nd Ed, Addison-Wesley, 2000, ISBN: 0-201-67519-6.

  20. What about unsigned numbers? • Conditional branch instructions blt, ble, bgt, etc, assume signed operands (defined as int in C). The equivalent instructions for unsigned operands (defined as unsigned in C). are: • blo Branch Lower (unsigned) • bls Branch Less or Same (unsigned) • bhi Branch Higher (unsigned) • bhs Branch Higher or Same (Unsigned) • v1 = FFFF FFFAhex, v2 = 0000 FFFAhex • What is result of cmp v1, v2 cmp v1, v2 bgt L1 bhi L1

  21. Signed VS Unsigned Comparison • v1 = FFFF FFFAhex, v2 = 0000 FFFAhex • v1 < v2 (signed interpretation) • v1 > v2 (unsigned interpretation) • What is result of cmp v1, v2 cmp v1, v2 bgt L1 bhi L1 … … L1: L1: Branch Taken Branch NOT taken

  22. Branches: PC-relative addressing • Recall register r15 in the machine also called PC; • points to the currently executing instruction • Most instruction add 4 to it. (pc increments by 4 after execution of most instructions) • Branch changes it to a specific value • Branch adds to it • 24-bit signed value (contained in the instruction) • Shifted left by 2 bits • Labels => addresses memory 0: b address –32MB 24 bits beq address registers +32MB r15 = pc r14 r0 FFF...

  23. C case/switch statement • Choose among four alternatives depending on whether k has the value 0, 1, 2, or 3 switch (k) { case 0: f=i+j; break; /* k=0*/ case 1: f=g+h; break; /* k=1*/ case 2: f=g–h; break; /* k=2*/ case 3: f=i–j; break; /* k=3*/ }

  24. Case/switch via chained if-else, C • Could be done like chain of if-else if(k==0) f=i+j; else if(k==1) f=g+h; else if(k==2) f=g–h; else if(k==3) f=i–j;

  25. Case/switch via chained if-else, C/Asm. • Could be done like chain of if-else if(k==0) f=i+j; else if(k==1) f=g+h; else if(k==2) f=g–h; else if(k==3) f=i–j; (f,i,j,g,h,k:v1,v2,v3,v4,v5,v6)cmp v6,#0 bne L1 ; branch k!=0add v1,v2,v3 ; k=0 so f=i+j b Exit ; end of caseL1:cmp v6,#1 bne L2 ; branch k!=1add v1,v4,v5;k=1 so f=g+h b Exit ; end of caseL2:cmp v6,#2 bne L3 ; branch k!=2sub v1,v4,v5 ; k=2 so f=g-h b Exit ; end of caseL3:cmp v6,#3 bne Exit ; branch k!=2 sub v1,v2,v3 ; k=3 so f=i-j Exit: C A R M

  26. Case/Switch via Jump Address Table • Notice that last case must wait for n-1 tests before executing, making it slow • Alternative tries to go to all cases equally fast: jump address table • Idea: encode alternatives as a table of addresses of the cases • Table an array of words with addresses corresponding to case labels • Program indexes into table and jumps • ARM instruction “ldr pc, [ ]” unconditionally branches to address L1 (Changes PC to address of L1)

  27. Idea for Case using Jump Table • check within range • get address of target clause from target array • jump to target address code for clause jump to end_of_case Address Jump Table Default clause end_of_case:

  28. Case/Switch via Jump Address Table (#1/3) • Use k to index a jump address table, and then jump via the value loaded • 1st test that k matches 1 of cases (0<=k<=3); if not, the code exits (k:v6, v7: Base address of JumpTable[k]) cmp v6, #0 ;Test if k < 0blt Exit ;if k<0,goto Exitcmp v6, #3 ;Test if k >3bgt Exit ;if k>3,goto Exit

  29. v7 L0 L1 L2 V6*4 L3 Case/Switch via Jump Address Table (#2/3) • Assume 4 sequential words (4 bytes) in memory, with base address in v7, have addresses corresponding to labels L0, L1, L2, L3. • Now use (4*k) (k:v6) to index table of words and load the clause address from the table (Address of labels L0, L1, L2, L3 ) to register pc. ldr pc, [v7, v6,lsl #2] ;JumpTable[k]= v7 + (v6*4) (Register Indexed Addressing) • PC will contain the address of the clause and execution starts from there.

  30. Case/Switch via Jump Address Table (#3/3) • Cases jumped to by ldr pc, [v7, v6,lsl #2] : L0: add v1,v2,v3;k=0 so f=i+j b Exit ; end of case L1: add v1,v4,v5;k=1 so f=g+h b Exit ; end of case L2:sub v1,v4,v5 ; k=2 so f=g-h b Exit ; end of caseL3:sub v1,v2,v3 ; k=3 so f=i-jExit:

  31. Jump Address Table: Summary (k,f,i,j,g,h Base address of JumpTable[k]) :v6,v1,v2,v3,v4,v5,v7) cmp v6, #0 ;Test if k < 0blt Exit ;if k<0,goto Exitcmp v6, #3 ;Test if k >3bgt Exit ;if k>3,goto Exit ldr pc, [v7, v6,lsl #2] ;JumpTable[k]= v7 + (v6*4) L0: add v1,v2,v3;k=0 so f=i+j b Exit ; end of case L1: add v1,v4,v5;k=1 so f=g+h b Exit ; end of case L2:sub v1,v4,v5 ; k=2 so f=g-h b Exit ; end of caseL3:sub v1,v2,v3 ; k=3 so f=i-jExit: More example on Jump Tables on CD-ROM

  32. If there is time, do it yourself: • Compile this C code into ARM: sum = 0; for (i=0;i<10;i=i+1) sum = sum + A[i]; • sum:v1, i:v2, base address of A:v3

  33. (If time allows) Do it yourself: C sum = 0; for (i=0;i<10;i=i+1) sum = sum + A[i]; • sum:v1, i:v2, base address of A:v3 mov v1, #0 mov v2, #0 Loop: ldr a1,[v3,v2,lsl #2] ; a1=A[i] add v1, v1, a1 ; sum = sum+A [i] add v2, v2, #1 ; increment i cmp v2, #10 ; Check(i<10)bne Loop ; goto loop A R M

  34. 28 24 20 16 4 0 31 12 8 N Z C V xx0x OR x1xx = C clear or Z set (unsigned lower or same)(ls) Cmp Instructions and CPSR Flags (#1/3) cmp r1, r2 ;Update flags after r1–r2 CPSR x1xx = Z set (equal)(eq) x0xx = Z clear (not equal)(ne) xx1x = C set (unsigned higher or same) (hs/cs) xx0x = C clear (unsigned lower) (lo/cc) x01x = C set and Z clear (unsigned higher)(hi) 1xxx = N set (negative) (mi) 0xxx = N clear (positive or zero) (pl)

  35. 28 24 20 16 4 0 31 12 8 N Z C V N = V (signed greater or equal (ge) N  V (signed less than) (lt) Z clear AND (N =V) (signed greater than) (gt) Cmp Instructions and CPSR Flags (#2/3) cmp r1, r2 ;Update flags after r1–r2 CPSR xxx1 = V set (signed overflow)(vs) xxx0 = V clear (signed no overflow) (vc) 1xx1 = N set and V set (signed greater or equal (ge) 0xx0 = N clear and V clear (signed greater or equal)(ge) 1xx0 = N set and V clear (signed less than) (lt) 0xx1 = N clear and V set (signed less than) (lt) 10x1 = Z clear, and N set and V set (signed greater)(gt) 00x0 = Z clear, and N clear and V clear (signed greater) (gt)

  36. 28 24 20 16 4 0 31 12 8 N Z C V Z set OR N  V (signed less or equal)(lt) cmp Instructions and CPSR Flags (#3/3) cmp r1, r2 ;Update flags after r1–r2 CPSR x1xx = Z set (equal)(eq) 1xx0 = N set and V clear (signed less) (le) 0xx1 = N clear and V set (signed less) (le)

  37. Example • Assuming r1 = 0x7fffffff, and r2 = 0xffffffff What the CPSR flags would be after the instruction; cmp r1, r2 Answer: r1 = 2147483647 r2 = (4294967295)or(-1) (Unsigned) (signed) r1- r2 = 0x7fff ffff - 0xffff ffff r1- r2 = 0x7fff ffff + - 0xffff ffff r1- r2 = 0x7fff ffff + 0x0000 0001 2’s complement of 0xffff ffff 0x8000 0000 (carry into msb  carry out of msb) 0(carry out) N=1, Z= 0, C = 0, V=1 C clear  (unsigned lower) (lo/cc) Z clear AND (N =V)  (signed greater than) (gt) 2147483647 > -1

  38. 28 24 23 20 16 4 0 31 12 8 L 24-bit signed offset 101 COND Branch Instruction Conditional Execution Field cmp r1, r2 B{<cont>} xyz 1001 = LS - C clear or Z set (unsigned lower or same) 1010 = GE - N set and V set, or N clear and V clear (signed >or =) 1011 = LT - N set and V clear, or N clear and V set (signed <) 1100 = GT - Z clear, and either N set and V set, or N clear and V clear (signed >) 1101 = LE - Z set, or N set and V clear,or N clear and V set (signed <, or =) 1110 = AL - always 1111 = NV - reserved. 0000 = EQ - Z set (equal) 0001 = NE - Z clear (not equal) 0010 = HS / CS - C set (unsigned higher or same) 0011 = LO / CC - C clear (unsigned lower) 0100 = MI -N set (negative) 0101 = PL- N clear (positive or zero) 0110 = VS - V set (overflow) 0111 = VC - V clear (no overflow) 1000 = HI - C set and Z clear (unsigned higher)

  39. Flag Setting Instructions • Compare cmp r1, r2 ; Update flags after r1 – r2 • Compare Negated cmn r1, r2 ; Update flags after r1 + r2 • Test tst r1, r2 ; Update flags after r1 AND r2 • Test Equivalence teq r1, r2 ; Update flags after r1 EOR r2 These instructions DO NOT save results; Only UPDATE CPSR Flags

  40. Flag Setting Instructions Example • Assuming r1 = 0x7fffffff, and r2 = 0xffffffff What would the CPSR flags would be after the instructions cmp r1, r2, lsl #2 cmn r1, r2, lsl #2 tst r1, r2, lsr #1 teq r1, r2, lsr #1

  41. Flag Setting Instructions Example Solution (#1/4) cmp r1, r2, lsl #2 Answer: r1 = 0x7fffffff = 2147483647 r2 lsl #2 =0xfffffffc = 4294967292 (unsigned) = (-4) (signed) r1 - r2 lsl # 2 = 0x7fff ffff + 0x0000 0100 2’s complement of 0xffff fffc 0x8000 00ff (carry into msb  carry out of msb) 0(carry out) N=1, Z= 0, C = 0, V = 1 C clear  (unsigned lower) (lo/cc) 2147483647 < 4294967292 Z clear AND (N = V)  (signed greater than) (gt) 2147483647 > -4

  42. Flag Setting Instructions Example Solution (#2/4) cmn r1, r2, lsl #2 Answer: r1 = 0x7fffffff = 2147483647 r2 lsl #2 =0xfffffffc = 4294967292 (unsigned) = (-4) (signed) r1 + r2 lsl # 2 = r1 – (-r2) (comparing r1 and –r2) 0x7fff ffff + 0xffff fffc 0x7fff fffb (carry into msb = carry out of msb) 1(carry out) N = 0, Z= 0, C = 1, V = 0 C set  (unsigned higher or same) (hs/cc). C set here really means there was an unsigned addition overflow Z clear AND (N = V)  (signed greater than) (gt) 2147483647 > -(-4) = 4

  43. Destination C 0 lsr Flag Setting Instructions Example Solution (#3/4) tst r1, r2, lsr #1 Answer: r1 = 0x7fffffff r2 lsr #1 =0x7fffffff r1 and r2 lsr # 1 = 0x7fff ffff and 0x7fff ffff 0x7fff ffff N = 0, Z= 0, C = 1, V= 0 N clear  (Positive or Zero) (pl) Z clear  (Not Equal) (ne). It really means ANDing of r1 and r2 does not make all bits 0 , ie r1 AND r2  0

  44. Destination C 0 lsr Flag Setting Instructions Example Solution (#4/4) teq r1, r2, lsr #1 Answer: r1 = 0x7fffffff r2 lsr #1 =0x7fffffff r1 eor r2 lsl # 1 = 0x7fff ffff xor 0x7fff ffff 0x0000 0000 N = 0, Z= 1, C = 1, V= 0 N clear  (Positive or Zero) (pl) Z set  (Equal) It really means r1 = r2

  45. Updating CPSR Flags with Data Processing Instructions • By default, data processing operations do not affect the condition flags • add r0,r1,r2; r0 = r1 + r2 ; ... and DO not set ; flags • To cause the condition flags to be updated, the “S” bit of the instruction needs to be set by postfixing the instruction with an “S”. • For example to add two numbers and set the condition flags: • adds r0,r1,r2; r0 = r1 + r2 ; ... and DO set flags

  46. Updating Flags Example • Compile this C code into ARM: sum = 0; for (i=0;i<10;i=i+1) sum = sum + A[i]; • sum:v1, i:v2, base address of A:v3

  47. Updating Flags Example Solution Ver 1 C sum = 0; for (i=0;i<10;i=i+1) sum = sum + A[i]; • sum:v1, i:v2, base address of A:v3 mov v1, #0 mov v2, #0 Loop: ldr a1,[v3,v2,lsl #2] ; a1=A[i] add v1, v1, a1 ;sum = sum+A [i] add v2, v2, #1 ;increment i cmp v2, #10 ; Check(i<10)bne Loop ; goto loop A R M

  48. Updating Flags Example Solution Ver 2 C sum = 0; for (i=0;i<10;i=i+1) sum = sum + A[i]; • sum:v1, i:v2, base address of A:v3 mov v1, #0 mov v2, #9 ; start with i = 9 Loop: ldr a1,[v3,v2,lsl #2] ; a1=A[i] add v1, v1, a1 ;sum = sum+A [i] sub v2, v2, #1 ;decrement i cmp v2, #0 ; Check(i<0)bge Loop ; goto loop A R M

  49. Updating Flags Example Solution Ver 3 C sum = 0; for (i=0;i<10;i=i+1) sum = sum + A[i]; • sum:v1, i:v2, base address of A:v3 mov v1, #0 mov v2, #9 ; start with i = 9 Loop: ldr a1,[v3,v2,lsl #2] ; a1=A[i] add v1, v1, a1 ; sum = sum+A [i] subs v2, v2, #1 ; decrement i ; update flagsbge Loop ; goto loop A R M

  50. COMP3221 Reading Materials (Week #5) • Week #5: Steve Furber: ARM System On-Chip; 2nd Ed, Addison-Wesley, 2000, ISBN: 0-201-67519-6. We use chapters 3 and 5 • ARM Architecture Reference Manual –On CD ROM

More Related