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FPGA based instrumentation for Correlators, Spectrometers, and VLBI(how to build eight radio astronomy instruments in two years) Dan Werthimer University of California, Berkeley http://seti.berkeley.edu
Our research group is really 3 groups • SETI (plus primordial black holes, HI mapping) • Public Participation Scientific Computing • CASPER – Center for Astronomy Signal Processing and Electronics Research
SETI@home Statistics TOTAL RATE
Public Participation Supercomputing Group David Anderson, Rom Walton, SETI Group • aka Distributed Computing • aka “edge resource aggregation”)
BOINC: NSF • Berkeley Open Infrastructure for Network Computing • General-purpose distributed computing framework. • Open source. • Will make distributed computing accessible to those who need it. (Starting from scratch is hard!)
Projects • Astronomy • SETI@home (Berkeley) • Astropulse (Berkeley) • Einstein@home: gravitational pulsar search (Caltech,…) • PlanetQuest (SETI Institute) • Stardust@home (Berkeley, Univ. Washinton,…) • Earth science • Climateprediction.net (Oxford) • Biology/Medicine • Folding@home, Predictor@home (Stanford, Scripts) • FightAIDSathome: virtual drug discovery • Physics • LHC@home (Cern) • Other • Web indexing/search • Internet Resource mapping (UC Berkeley)
Where's the computing power? your computers home PCs academic business • 2010: 1 billion Internet-connected PCs • 55% privately owned • If 100M participate: • 100 PetaFLOPs, 1 Exabyte (10^18) storage
CASPER: Center for Radio Astronomy Signal Processing and Electronics Research Henry Chen, Daniel Chapman, Pat Crescini, Pierre Droz, Kirsten Meder, Vinayak Nagpal, Arash Parsa, Aaron Parsons, Andrew Siemion, Dan Werthimer Radio Astronomy Lab: Don Backer, Paul Demorest, Matt Dexter, Carl Heiles, David McMahon, Mel Wright, Lynn Urry Berkeley Wireless Research Center: Bob Broderson, Chen Chang, John Wawrzynek SETI Institute: Dave Deboer, Gerry Harp Collaborators: Jeff Mock, NAIC, NRAO, ATNF, JPL/DSN, Harvard/Smithsonian/CFA, MIT/Haystack, GMRT, Caltech, South Africa KAT
CASPER Real-time Signal Processing Instrumentation(NSF ATI, MRI) • Low NRE, shared by the community • Rapid development (8 instruments / 2 years) • Open-source, collaborative • Reusable, platform-independent gateware • Modular, upgradeable hardware • Industry standard communication protocols • Low Cost
MOTIVATIONATA, SKA, Focal Plane Arrays, SETI,need >> PetaOp/sec Instruments take a long time to build, very high NRE
MWA XNTD PAPER FAST PAST LAR LWA The Radio Revolution
Allen Telescope Array • 6.1-meter offset Gregorian (2.4-meter secondary)
The Problem with the CurrentHardware Development Model • Takes 5 years • Cost Dominated by NRE because of custom Boards, Backplanes, Protocols • Antiquated by the time it’s released.
Solution: • Modular Hardware • Low number of board designs • Can be upgraded piecemeal or all together • Reusable • Standard signal processing model which is consistent between upgrades.
Solution: use FPGA’s1 FPGA = 100 Pentium, 1/500 the power per op Moores Law for FGPA’s 3X improvement per year!
Platform-Independent, Parameterized Gateware • What is Gateware? • Design logic of FPGAs (between hardware and software) • Need libraries for signal processing which don’t have to be rewritten every hardware generation. • Matlab Simulink!
Biplex Pipelined FFT • Uses 1/6 the resources of the Xilinx module.
FFT controls Simulink Library – Aaron Parsons • Verilog Library – Jeff Mock • Transform length • Bandwidth • Complex or Real • Number of Polarizations • Input bit width and output bit width • twiddle coefficient bit width • Run-time programmable down-shifting • Decimate option
Filter Response: PFB vs. FFT
Additional PFB controls • (Aaron Parsons, Jeff Mock) • Filter overlap • Width of filter coefficients • Window function for filter (hamming, hanning, etc.) • Import filter coefficients for custom filter performance
Digital Down-Converter • Selectable # of FIR taps • On-the-fly programmable mix frequency • Selectable FIR coeff • Agile sub-band selection.
Global Interconnects • Commercial 10GBe switch from HP, Fujitsu, Foundry, Extreme Networks, Force 10 • Packet switched, non-blocking • <= 224 ports (4X) per chassis • Up to 10,000 ports in a system • 200~1000 ns switch latency • 400~1200 ns FPGA to FPGA latency • ~ 2.88Tbps full duplex constant cross section bandwidth • $600 per port
BeowulfCluster Like General Purpose Architechture Dynamic Allocation of Resources, need not be FPGA based
Targeted Applications • Moderate to high-bandwidth problems • For low bandwidths, just use CPUs • Lower to mid-scale computation • For very large applications (SKA), may be more cost effective to design ASICs • Rapid Development
Applications • VLBI Mark 5B data recorder - Haystack – 500 MHz • Beamforming – SMA – Vinayak Nagpal, Jonathan Weintroub • SETI – Arecibo (UCB) JPL/UCB DSN (Preston, Gulkis, Levin, Jones) • Correlators and Imagers: ATA (Mel Wright) Reionization Experiment (Backer, Bradley…) Carma Next Gen (Dave Hawkins, Caltech) SKA demonstrator South Africa (Justin Jonas)
VLBI Digitizer-Channelizer for Mark5Haystack: Shep Doeleman, Brian Fanous, Alan Rogers, Alan Whitney UCB: Henry Chen, Aaron Parsons, Pierre Droz • Interfaces to MARK 5 data recorder • 500 MHz bandwidth * 2 IF’s (Only 1 IF now) • 16 or 32 channels per IF • Polyphase Filter Bank