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HomeWork 6 & 7

HomeWork 6 & 7. Fang Gong gongfang@ucla.edu. Problem Formulation: Large circuit can be partitioned into relatively independent blocks, and each block has multiple ports. Each port can be modeled as a time-varying current source.

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HomeWork 6 & 7

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  1. HomeWork 6 & 7 Fang Gong gongfang@ucla.edu

  2. Problem Formulation: Large circuit can be partitioned into relatively independent blocks, and each block has multiple ports. Each port can be modeled as a time-varying current source. This homework tries to extract the temporal correlation between currents for a particular port. Given the peak current in every clock cycle at a particular port, (1) compute the temporal correlation coefficient between currents: in adjacent clock cycles two clock cycles apart. (2) Also find the number of clock cycles that gives the maximum correlation coefficient, which corresponds to the number of clock cycles used to execute instructions. HW6Temporal correlation estimation for switching currents.[Due on March 9]

  3. Steps 1. Store the data in a MATLAB variable v1. 2. Shift the variable by one clock cycle and store it in a new variable v2 3. Truncate v1 so that v1 and v2 has the same length. 4. Compute the correlation coefficient: corrcoef(v1,v2) 5. This gives the current correlation between adjacent clock cycles. 6. Shift v1 by two clock cycles and store it in a new variable v3. 7. Repeat steps 3-5 to get the correlation coefficients. This is the current correlation two clock cycles apart. 8. Do this for different number of clock cycles, and plot the figure. 9. Pick out the number of clock cycles that gives the maximum correlation coefficients. 3

  4. HW7: Problem 1: Impedance of Package Power Distribution Network [Due on March 16] • Power Distribution Network (PDN) can be presented as above. • Voltage Regulator Module (VRM) • Package Plane Capacitance • Ball Grid Array (BGA) • Die Parasitic and On-die Decoupling Capacitance • (ZPDN) is the impedance of the PDN associated with the path from a voltage regulator module (VRM) to the Die. equivalent circuit model • Problem: • Please plot the impedance (ZPDN) observed from die v.s. frequency. • Indicate that at which frequency ZPDN has its peak value and the magnitude of peak value.

  5. HW7: Problem 2: Designing Target Impedance of a PDN [Due on March 16] • To lower the noise (voltage ripple), the goal of a power distribution network system design is to have impedance (ZPDN) that is low with a flat response over a desired frequency range. • On-package decoupling capacitors are usually used and can be modeled as a series combination of • the equivalent series inductance (ESL) • capacitance of the capacitor (C). • the equivalent series resistance (ESR).

  6. Problem 2: Question 1 • Q1: Assume only one type of decap is available with C=200nF, ESL=100pH, and ESR=60 mΩ and at most 30 decaps can be used. • Problem: • Using this type of decap, please try to show whether it is possible to make the overall ZPDN less than 50 mΩ over frequency range from 2MHz to 1GHz? • If it can, show how many decaps can be used. If it cannot, explain why.

  7. Problem 2: Question 2 • Q2: In addition to the decap used in (a), assume a second type of decap (from the table below) can be used to make ZPDN less than 50 mΩ over frequency range from 2MHz to 1GHz. • Problem: • Please choose one type decap out of the following candidates that can help you achieve this goal. • Plot the final overall impedance response over above-mentioned frequency range and show how many for each type of decaps are used in your final design. (totally maximum 30 decaps are allowed.)

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