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The Microarchitecture Level. Chapter 4. The Data Path (1). The data path of the example microarchitecture used in this chapter. The Data Path (2). Useful combinations of ALU signals and the function performed. Data Path Timing. Timing diagram of one data path cycle. Memory Operation.

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the microarchitecture level

The Microarchitecture Level

Chapter 4

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

the data path 1
The Data Path (1)

The data path of the example

microarchitecture used in this

chapter.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

the data path 2
The Data Path (2)

Useful combinations of ALU signals and the function performed.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

data path timing
Data Path Timing

Timing diagram of one data path cycle.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

memory operation
Memory Operation

Mapping of the bits in MAR to the address bus.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

microinstructions
Microinstructions

The microinstruction format for the Mic-1.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

microinstruction control the mic 1 1
Microinstruction Control: The Mic-1 (1)

The complete block

diagram of our example

microarchitecture, the

Mic-1.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

microinstruction control the mic 1 2
Microinstruction Control: The Mic-1 (2)

A microinstruction with JAMZ set to 1 has two potential successors.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

stacks 1
Stacks (1)

Use of a stack for storing local variables.

  • While A is active. b) After A calls B.
  • (c) After B calls C. d) After C and B return and A calls D.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

stacks 2
Stacks (2)

Use of an operand stack for doing an arithmetic computation.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

the ijvm memory model
The IJVM Memory Model

The various parts of the IJVM memory.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

the ijvm instruction set 1
The IJVM Instruction Set (1)

The IJVM instruction set. The operands byte, const, and varnum

are 1 byte. The operands disp, index, and offset are 2 bytes.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

the ijvm instruction set 2
The IJVM Instruction Set (2)
  • Memory before executing INVOKEVIRTUAL.
  • After executing it.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

the ijvm instruction set 3
The IJVM Instruction Set (3)
  • Memory before executing IRETURN.
  • After executing it.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

compiling java to ijvm 1
Compiling Java to IJVM (1)
  • A Java fragment.
  • The corresponding Java assembly language.
  • The IJVM program in hexadecimal.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

compiling java to ijvm 116
Compiling Java to IJVM (1)

The stack after each instruction of Fig. 4-14(b).

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

microinstructions and notation
Microinstructions and Notation

All permitted operations. Any of the

above operations may be extended

by adding ‘‘<< 8’’ to them to shift the

result left by 1 byte. For example,

a common operation is

H = MBR << 8

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

implementation of ijvm using the mic 1 1
Implementation of IJVM Using the Mic-1 (1)

The microprogram for the Mic-1

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

implementation of ijvm using the mic 1 2
Implementation of IJVM Using the Mic-1 (2)

The microprogram for the Mic-1

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

implementation of ijvm using the mic 1 3
Implementation of IJVM Using the Mic-1 (3)

The microprogram for the Mic-1

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

implementation of ijvm using the mic 1 4
Implementation of IJVM Using the Mic-1 (4)

The microprogram for the Mic-1

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

implementation of ijvm using the mic 1 5
Implementation of IJVM Using the Mic-1 (5)

The microprogram for the Mic-1

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

implementation of ijvm using the mic 1 6
Implementation of IJVM Using the Mic-1 (6)

The BIPUSH instruction format.

  • ILOAD with a 1-byte index.
  • WIDE ILOAD with a 2-byte index.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

implementation of ijvm using the mic 1 7
Implementation of IJVM Using the Mic-1 (7)

The initial microinstruction

sequence for ILOAD

and WIDE ILOAD. The

addresses are examples.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

implementation of ijvm using the mic 1 8
Implementation of IJVM Using the Mic-1 (8)

The IINC instruction has two different operand fields.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

implementation of ijvm using the mic 1 9
Implementation of IJVM Using the Mic-1 (9)

The situation at the start of various microinstructions.

a) Main1. b) goto1. c) goto2. d) goto3. e) goto4.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

speed versus cost
Speed Versus Cost
  • Reduce the number of clock cycles needed to execute an instruction.
  • Simplify the organization so that the clock cycle can be shorter.
  • Overlap the execution of instructions.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

merging the interpreter loop with the microcode 1
Merging the Interpreter Loop with the Microcode (1)

Original microprogram sequence for executing POP.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

merging the interpreter loop with the microcode 2
Merging the Interpreter Loop with the Microcode (2)

Enhanced microprogram sequence for executing POP.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

a three bus architecture 1
A Three Bus Architecture (1)

Mic-1 code for executing ILOAD.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

a three bus architecture 2
A Three Bus Architecture (2)

Three-bus code for executing ILOAD.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

a three bus architecture 3
A Three Bus Architecture (3)

A fetch unit for the Mic-1.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

a three bus architecture 4
A Three Bus Architecture (4)

A finite state machine for implementing the IFU.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

a three bus architecture 5
A Three Bus Architecture (5)

The data path for

Mic-2.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

a pipelined design the mic 3 1
A Pipelined Design: The Mic-3 (1)

The microprogram for the Mic-2

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

a pipelined design the mic 3 2
A Pipelined Design: The Mic-3 (2)

The microprogram for the Mic-2

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

a pipelined design the mic 3 3
A Pipelined Design: The Mic-3 (3)

The microprogram for the Mic-2

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

a pipelined design the mic 3 4
A Pipelined Design: The Mic-3 (4)

The microprogram for the Mic-2

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

three bus architecture
Three BusArchitecture

The three-bus data path used

in the Mic-3.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

implementation of swap 1
Implementation of SWAP (1)

The Mic-2 code for SWAP.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

implementation of swap 2
Implementation of SWAP (2)

The implementation of SWAP on the Mic-3.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

pipeline
Pipeline

Graphical illustration of

how a pipeline works.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

a seven stage pipeline the mic 4 1
A Seven-Stage Pipeline: The Mic-4 (1)

The main components of the Mic-4.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

a seven stage pipeline the mic 4 2
A Seven-Stage Pipeline: The Mic-4 (2)

The Mic-4 pipeline.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

cache memory
Cache Memory

A system with three levels of cache.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

direct mapped caches
Direct-Mapped Caches

(a) A direct-mapped cache. (b) A 32-bit virtual address.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

set associative caches
Set-Associative Caches

A four-way set-associative cache.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

branch prediction
Branch Prediction

(a) A program fragment. (b) Its translation to a generic assemblylanguage.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

dynamic branch prediction 1
Dynamic Branch Prediction (1)

(a) A 1-bit branch history. (b) A 2-bit branch history. (c) A mapping

between branch instruction address and target address.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

dynamic branch prediction 2
Dynamic Branch Prediction (2)

A 2-bit finite-state machine for branch prediction.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

out of order execution and register renaming 1
Out-of-Order Execution and Register Renaming (1)

A superscalar CPU with in-order issue and in-order completion.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

out of order execution and register renaming 2
Out-of-Order Execution and Register Renaming (2)

A superscalar CPU with in-order issue and in-order completion.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

out of order execution and register renaming 3
Out-of-Order Execution and Register Renaming (3)

Operation of a superscalar CPU with out-of-order issue

and out of-order completion.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

speculative execution
Speculative Execution
  • A program fragment.
  • The corresponding basic block graph.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

overview of the netburst microarchitecture
Overview of the NetBurst Microarchitecture

The block diagram of the Pentium 4.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

the netburst pipeline
The NetBurst Pipeline

A simplified view of

the Pentium 4 data

path.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

overview of the ultrasparc iii cu microarchitecture
Overview of the UltraSPARC III Cu Microarchitecture

The block diagram of the UltraSPARC III Cu.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

ultrasparc iii cu pipeline
UltraSPARC III Cu Pipeline

A simplified

representation of the

UltraSPARC III Cu

pipeline.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

the microarchitecture of the 8051 cpu
The Microarchitecture of the 8051 CPU

The microarchitecture

of the 8051.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0