SAJE SiliconAid JTAG Environment

1. SAJE SiliconAid JTAG Environment Overview – Very Short

2. SAJE JTAG Product Summary Synthesis Verification Debugger JTS JTV JTD Generate P1687 JTAG Designs Verify BSDL and JTAG Design Provide JTAG Debug environment

3. P1687 Activities • YES – P1687 Exists and works • SiAid is making significant investment • Alpha software demos available • Beta Software in development • Partnering with key companies

4. P1687 Simplified Basic Flow Wrap IP Wrap Existing IPswith1500 wrapper and enhance for P1687 Automatically integrate wrapped IP, insert JTAG with P1687 compliant structures P1687 Synthesis Convert Wrapped IP vectors into Chip level JTAG patterns Pattern Conversion Verify JTAG and generate testbench to sim all test including IP patterns Generate Testbench Simulate

5. The BIG PICTURE Insert JTAG and 1687 Logic JTS Generate Simulation and Chip Vectors Exhaustive semantic and compliance checking JTV Subset of Patterns for Board level support (SVF) BOARD Simulate CHIP (JTD) Verify JTAG and generate testbench to sim all test including IP patterns Leverages Design data to drive and debug JTAG hardware Matches Vectors by Vector: Simulation, CHIP, and BOARD

6. Board SVF Debug Flow Board Test Board Test Fails Verify JTAG and generate testbench to sim all test including IP patterns Generate Patterns Debugger Simulate

7. JTV - Typical ATE Flow Company A BSDL J T V STIL Vector file • No Verilog Netlist • No Simulation Your Specific Guidelines

8. 1687 Network GUI Serial ATPG

9. 1687 Board SVF Debug Flow Board Test Board Test Fails 1687 ATPG Understands 1687 network and BSDL, Generates selected tests, SVF output Board or ATE Debugger Interactive debugger – leverages design info into ATE and Board tests

10. SiliconAid Solutions JTAG DEBUGGER TOOL (JTD)

11. WHY JTD • New Product Introduction/Evaluation • Proto-typing pre-Silicon on Xilinx Boards • Works in concert with ATE testers • Debug capabilities to identify internal registers failing on TDO • Tracks JTAG state machine on vector per vector basis • Fast, easy, quick way to drive and observe standard JTAG signals • Leverages JTV output to enhance debugging capability

12. JTD Major Features • Hardware Interface using USB 2.0 • JTAG 5 pin connector • Can drive evaluation board, Apps board, burn in board, ATE tester board, and more….. • Compares expected values for TD0 • Supports run till FAIL, STEP, etc.. • Leverages patterns from JTV • Supports external SVF patterns

13. Initial JTD Window Debugger run and controls patterns JTAG State Machine Viewer Online Help and apps notes Displays Fails on actual register Displays expected and actual data in waveforms

14. Debugger Window Flow Control Header Info Fails Results Window log Window Command line

15. Register Viewer Failing bits are graphically displayed and bit descriptions pop up when clicked. Black – Expect 1 White – Expect 0 Red - Failed

16. Waveform Viewer Capturing internal registers not accessible via pins on the device.

17. JTAG State Machine Status Status is graphically displayed real time as the vectors are steps in the debugger window

18. JTD Apps Board DEMO USB 2.0 JTAG Signals TMS TDI TDO TCK TRST

19. What is JTV ?

20. SiliconAid Solutions JTAG VERIFICATION TOOL (JTV)

21. JTV - Purpose • Verification support for JTAG providers • Focus is chip-level verification • Provide an efficient means to • Insure correct JTAG functionality on first-pass silicon • Deliver a verified BSDL file for customer usage • Deliver high quality production test vectors • Diagnose fab-related pad or JTAG logic yield problems • Goal is to • Eliminate customer BSDL and/or JTAG-related problems

22. JTV Design Flow Diagram

23. SAJE JTV simplified Flow BSDL JTAG Generation • Legacy Designs • Any 3rd Party tool • Internally developed SAJE JTV • Independent verification that BSDL matches your Design • Verifies Design is IEEE 1149.1 & 1149.6 compliant • Generates full suite of Production test vectors • Generates verilog testbench & tests for verification • Proven technology on hundreds of production designs • More than 12 years + of success Netlist with JTAG Production Ready Patterns User selectable test Testbench Any 3rd Party Simulator

24. Board Companies Specific Benefits • Screen for incoming BSDL • Chip level ATE pattern • Board Level targeted patterns for a chip • No Verilog required • Standardized test bench for all incoming design (if chip provider supplies verilog)

25. Incoming BSDL and Verilog Process Flow Company A J T V Company B Company X Checker Company C Company D Release to Production Company X Specific Guidelines

26. JTV - Typical ATE Flow Company A BSDL J T V STIL Vector file • No Verilog Netlist • No Simulation Company X Specific Guidelines

27. Summary • Simulation, ATE, and Board can have same patterns applied – Helps solve the NPF problems! • Alpha 1687 Flow available • JTD - Debugger works at chip level and plans to support board level in the future • JTV is a mature product with 15+ years of continual history and usage • 1149.1 and 1149.6 Chip verification and compliance checking • Verifies BSDL matches design • SVF Patterns will soon be portable to board test • Tools be used in a custom or JTAG synthesis design flow • Leverages Design data in ATE and Board Debug

28. Jim Johnson : President email: jim.johnson@siliconaid.com phone: (512) 694-4261