m5151117 Yumiko Kimezawa

1. RPR Design and realization of the hardware platform based on the Nios soft-core processorZuo Zhen, Tang Guilin, Dong Zhi, Huang Zhiping m5151117 Yumiko Kimezawa

2. Outline RPR • Introduction • Nios CPU Overview • Block Diagram of the Platform • Layout Practices • Conclusion

3. Introduction RPR • Since FPGA’s introduction in June 2000, Altera’s Nios soft-core processor has rapidly been integrated in a wide range of applications • Designers can tailor the Nios system with the exact peripherals provided by the library • The Nios system reveals the System-on-a-Programmable Chip (SOPC) design methodology

4. Nios CPU Overview RPR • A pipelined general-purpose RISC microprocessor • 32-bit and 16-bit architectural variants • 16 and 32-bit variants use 16-bit instructions • Users can incorporate custom logic directly into the Nios arithmetic logic unit (ALU) • It is easy to specify connections between such as memory and peripheral by using the SOPC Builder system design tool

5. Block Diagram of the Platform RPR • FPGA • Altera Cyclone EP1C12Q240C8 • The major feature of the platform • Power • A core voltage VCCINT(1.5V) and the I/O voltage VCCIO( 3.3V) power supply are needed • The TPS54316 and TPS54313* chip can output 3.3V and 1.5V respectively • Clocking • The simplest way to achieve clocking is to use a low-skew clock devicesuch a IDT74FCT3807/A chip which is a 1:10 low-skew clock distribution device *TPS5431x is low-input-voltage high-output-current synchronous-buck PWM converters Fig.2: Hardware Platform Block Diagram

6. Block Diagram of the Platform RPR • FPGA device • Through simulation, the EP1C12Q240C8 device of Altera Cyclone serials best suits author’s need • RS232 Serial Port • Implementing an RS232 serial connection to communicate with a HOST PC for debug • Connector • A transceiver that can driver signal should be adopted • The hardware platform also provides power supply to other circuit board through the connectors *TPS5431x is low-input-voltage high-output-current synchronous-buck PWM converters Fig.2: Hardware Platform Block Diagram

7. Block Diagram of the Platform RPR • 10/100 Base-T Ethernet Port • A 10/100 Base-T Ethernet port is designed, achieving high-speed data transport • The LAN91C111 device • is designed to facilitate the implementation of 3rd generation of Fast Ethernet connectivity solutions for embedded applications • can automatically configure itself for 100 or 10 Mbps and Full or Half Duplex operation with on-chip Auto-Negotiation algorithm the 10/100-Base-T port connector Fig. 3: Basic Functional Block Diagram of LAN91C111

8. Block Diagram of the Platform RPR • Memory • One piece of 8Mbytes Flash memory Intel E28F640J3A • High-density memories organized as 64128Kbytes erase blocks are contained • Its optimized architecture and interface dramatically increase read performance by supporting page-mode reads • Two piece of 512Kbytes SRAM memory IDT71V416S • The IDT71V416S is a 4,194,304bit high-speed Static RAM organized as 256K*16 • is fabricated using IDT’s high-performance, high-reliability CMOS technology • has an output enable pin which operates as fast as 5ns, with address access times as fast as 10ns Fig.4: Memory Interface Block Diagram

9. Layout Practices RPR • Decoupling is one of the most important aspects of board design • Decoupling capacitors should be located as close as possible to the four sides of the device package

10. Conclusion RPR • The design and realization of a hardware platform based on the Nios soft-core processor • The hardware platform consists of power, clocking, FPGA device, RS232 serial port, 10/100 Base-T Ethernet Port, memory and connector