# ELEC 7770 Advanced VLSI Design Spring 2010 Clock Skew Problem - PowerPoint PPT Presentation

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ELEC 7770 Advanced VLSI Design Spring 2010 Clock Skew Problem

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ELEC 7770 Advanced VLSI Design Spring 2010 Clock Skew Problem
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## ELEC 7770 Advanced VLSI Design Spring 2010 Clock Skew Problem

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1. ELEC 7770Advanced VLSI DesignSpring 2010Clock Skew Problem Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr10/course.html ELEC 7770: Advanced VLSI Design (Agrawal)

2. Single Clock FF A FF B Comb. Data_out Data_in CKA CKB CK CKA CKB Single-cycle path delay ELEC 7770: Advanced VLSI Design (Agrawal)

3. Multiple Clocks FF A FF B Comb. Data_out Data_in CKA CKB CKA CKB Multi-cycle path delay ELEC 7770: Advanced VLSI Design (Agrawal)

4. Clock Skew • Skew is the time delay of clock signal at a flip-flop with respect to some time reference. • For a given layout each flip-flop has a skew, measured with respect to the a common reference. • Skews of flip-flops separated by combinational paths affect the short-path and long-path constraints. ELEC 7770: Advanced VLSI Design (Agrawal)

5. Skews for Single-Cycle Paths Combinational Block Delay: FFi CKi FFj CKj δ(i,j) ≤ d(i,j) ≤ Δ(i,j) xi xj xi and xj are arrival times of clock edges ELEC 7770: Advanced VLSI Design (Agrawal)

6. Short-Path Constraint (Double-Clocking) Tck CKi si intended Not intended CKj Thj sj δ(i,j) si + δ(i,j) ≥ sj + Thj ELEC 7770: Advanced VLSI Design (Agrawal)

7. Long-Path Constraint (Zero-Clocking) Tck CKi si Not intended intended CKj sj Tsj Δ(i,j) si + Δ(i,j) ≤ sj + Tck – Tsj ELEC 7770: Advanced VLSI Design (Agrawal)

8. Maximum Clock Frequency Linear program: Minimize Tck Subject to: For all flip-flop pairs (i,j), si + δ(i,j) ≥ sj + Thj si + Δ(i,j) ≤ sj + Tck – Tsj ELEC 7770: Advanced VLSI Design (Agrawal)

9. Finding Clock Skews sk FFi FFj FFk si Ri Rj Rk CK Ci Cj Ck sj Use Elmore delay formula to calculate si, sj, sk. ELEC 7770: Advanced VLSI Design (Agrawal)

10. Interconnect Delay: Elmore Delay Model • W. Elmore, “The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers,” J. Appl. Phys., vol. 19, no.1, pp. 55-63, Jan. 1948. i Rj Ri Rk j k CK Ci Cj Ck Shared resistance: Rii = Ri Rij = Rji = Ri Rik = Rki = Ri Rjj = Ri + Rj Rjk = Rkj = Ri + Rj Rkk = Ri + Rj + Rk ELEC 7770: Advanced VLSI Design (Agrawal)

11. Elmore Delay Calculation Delay at node k, sk = 0.69 (Ci × Rik + Cj × Rjk + Ck × Rkk ) = 0.69 [Ri Ci + (Ri + Rj) Cj + (Ri + Rj + Rk)Ck] ELEC 7770: Advanced VLSI Design (Agrawal)

12. Finding δ(I,j) and Δ(I,j) Minimum delay Maximum delay , - , - A 1 , - 9, 10 H 3 j , - 0, 0 3, 3 B 3 4, 4 i E 1 G 2 6, 7 , - , - C 1 , - 6, 8 J 1 F 1 k , - , - 5, 5 D 2 , - ELEC 7770: Advanced VLSI Design (Agrawal)

13. Maximum Clock Frequency for Tolerance ±q/2 in Skew Linear program: Minimize Tck Subject to: For all flip-flop pairs (i,j), si + δ(i,j) ≥ sj + Thj + q si + Δ(i,j) ≤ sj + Tck – Tsj – q Where q is a constant si are variables, simin ≤ si Tck is a variable ELEC 7770: Advanced VLSI Design (Agrawal)

14. Maximum Tolerance for Given Clock Frequency Linear program: Maximize q Subject to: For all flip-flop pairs (i,j), si + δ(i,j) ≥ sj + Thj + q si + Δ(i,j) ≤ sj + Tck – Tsj – q Where Tck is a constant si are variables, simin ≤ si q is a variable ELEC 7770: Advanced VLSI Design (Agrawal)

15. Tradeoffs No solution because of zero slack. Increasing skew tolerance q Increasing clock period Tck ELEC 7770: Advanced VLSI Design (Agrawal)

16. Clock Skew Problem • N. Maheshwari and S. S. Sapatnekar, Timing Analysis and Optimization of Sequential Circuits, Springer, 1999. • J. P. Fishburn, “Clock Skew Optimization,” IEEE Trans. Computers, vol. 39, no. 7, pp. 945-951, July 1990. ELEC 7770: Advanced VLSI Design (Agrawal)