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CSE 3322 Computer Architecture Additional Assignments for Chapter 5 Due Mon Oct 25

CSE 3322 Computer Architecture Additional Assignments for Chapter 5 Due Mon Oct 25 1.    We wish to add the MIPS instruction addi ( add immediate) to the MIPS lite design we did in class. a. Write the Register Transfer Sequences that would implement this instruction.

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CSE 3322 Computer Architecture Additional Assignments for Chapter 5 Due Mon Oct 25

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  1. CSE 3322 Computer Architecture Additional Assignments for Chapter 5 Due Mon Oct 25 1.    We wish to add the MIPS instruction addi ( add immediate) to the MIPS lite design we did in class. a. Write the Register Transfer Sequences that would implement this instruction. b. Modify, if required, the ALU Control to implement this instruction c. Give the modified truth table for the ALU control signals and the States 2.     We wish to add the MIPS instruction jal (jump and link) to the MIPS lite design we did in class. a. Write the Register Transfer Sequences that would implement this instruction. b. Modify, if required, the PC Control to implement this instruction c. Give the modified truth table for the PC control signals and the States 3.     We wish to add the MIPS instruction lui (load upper immediate) to the MIPS lite design we did in class. a. Write the Register Transfer Sequences that would implement this instruction. b. Modify, if required, the Register File Control to implement this instruction c. Give the modified truth table for the Register File control signals and the States

  2. Multicycle Implementation I n s t r u c t i o n r e g i s t e r D a t a P C A d d r e s s IR A R e g i s t e r # I n s t r u c t i o n A L U A L U O u t M e m o r y R e g i s t e r s o r d a t a R e g i s t e r # M e m o r y d a t a B D a t a r e g i s t e r R e g i s t e r # MDR

  3. State Register Transfers S0 M[PC] IR, PC + 4 PC, S1 S

  4. State Register Transfers S0 M[PC] IR, PC + 4 PC, S1 S S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 S

  5. State Register Transfers S0 M[PC] IR, PC + 4 PC, S1 S S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 S S2 A + sign_ext(IR[15-0]) ALUOut, ‘LW’S3 + ‘SW’S5 S

  6. State Register Transfers S0 M[PC] IR, PC + 4 PC, S1 S S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 S S2 A + sign_ext(IR[15-0]) ALUOut, ‘LW’S3 + ‘SW’S5 S S3 M[ ALUOut] MDR, S4 S

  7. State Register Transfers S0 M[PC] IR, PC + 4 PC, S1 S S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 S S2 A + sign_ext(IR[15-0]) ALUOut, ‘LW’S3 + ‘SW’S5 S S3 M[ ALUOut] MDR, S4 S S4 MDR R[ IR[20-16]], S0 S

  8. State Register Transfers S0 M[PC] IR, PC + 4 PC, S1 S S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 S S2 A + sign_ext(IR[15-0]) ALUOut, ‘LW’S3 + ‘SW’S5 S S3 M[ ALUOut] MDR, S4 S S4 MDR R[ IR[20-16]], S0 S S5 B M[ ALUOut], S0 S

  9. State Register Transfers S0 M[PC] IR, PC + 4 PC, S1 S S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 S S2 A + sign_ext(IR[15-0]) ALUOut, ‘LW’S3 + ‘SW’S5 S S3 M[ ALUOut] MDR, S4 S S4 MDR R[ IR[20-16]], S0 S S5 B M[ ALUOut], S0 S S6 A op B ALUOut, S7 S

  10. State Register Transfers S0 M[PC] IR, PC + 4 PC, S1 S S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 S S2 A + sign_ext(IR[15-0]) ALUOut, ‘LW’S3 + ‘SW’S5 S S3 M[ ALUOut] MDR, S4 S S4 MDR R[ IR[20-16]], S0 S S5 B M[ ALUOut], S0 S S6 A op B ALUOut, S7 S S7 ALUOut R[IR[15-11]], S0 S

  11. State Register Transfers S0 M[PC] IR, PC + 4 PC, S1 S S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 S S2 A + sign_ext(IR[15-0]) ALUOut, ‘LW’S3 + ‘SW’S5 S S3 M[ ALUOut] MDR, S4 S S4 MDR R[ IR[20-16]], S0 S S5 B M[ ALUOut], S0 S S6 A op B ALUOut, S7 S S7 ALUOut R[IR[15-11]], S0 S S8 Zero PC + Zero ALUOut PC, S0 S

  12. State Register Transfers S0 M[PC] IR, PC + 4 PC, S1 S S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 S S2 A + sign_ext(IR[15-0]) ALUOut, ‘LW’S3 + ‘SW’S5 S S3 M[ ALUOut] MDR, S4 S S4 MDR R[ IR[20-16]], S0 S S5 B M[ ALUOut], S0 S S6 A op B ALUOut, S7 S S7 ALUOut R[IR[15-11]], S0 S S8 Zero PC + Zero ALUOut PC, S0 S S9 PC[31-28] : shlt2(IR[25-0]) PC, S0 S

  13. MEMORY CONTROL M[PC] IR M[ ALUOut] MDR B M[ ALUOut] Addr Read Data Write Data

  14. MEMORY CONTROL M[PC] IR M[ ALUOut] MDR B M[ ALUOut] MemRead Addr Read Data Write Data MemWrite

  15. MEMORY CONTROL M[PC] IR M[ ALUOut] MDR B M[ ALUOut] IorD MemRead PC 0 1 Addr Read Data ALUOut Write Data MemWrite

  16. MEMORY CONTROL M[PC] IR M[ ALUOut] MDR B M[ ALUOut] IRWrite IorD MemRead IR PC 0 1 Addr Read Data ALUOut Write Data B MDR MemWrite

  17. IorD IRWrite MemRead MemWrite S0 M[PC] IR S3 M[ ALUOut] MDR S5 B M[ ALUOut] IRWrite IorD MemRead IR PC 0 1 Addr Read Data ALUOut Write Data B MDR MemWrite

  18. IorD IRWrite MemRead MemWrite S0 M[PC] IR 0 1 1 0 S3 M[ ALUOut] MDR S5 B M[ ALUOut] IRWrite IorD MemRead IR PC 0 1 Addr Read Data ALUOut Write Data B MDR MemWrite

  19. IorD IRWrite MemRead MemWrite S0 M[PC] IR 0 1 1 0 S3 M[ ALUOut] MDR 1 0 1 0 S5 B M[ ALUOut] IRWrite IorD MemRead IR PC 0 1 Addr Read Data ALUOut Write Data B MDR MemWrite

  20. IorD IRWrite MemRead MemWrite S0 M[PC] IR 0 1 1 0 S3 M[ ALUOut] MDR 1 0 1 0 S5 B M[ ALUOut] 1 0 0 1 IRWrite IorD MemRead IR PC 0 1 Addr Read Data ALUOut Write Data B MDR MemWrite

  21. State Register Transfers S0 M[PC] IR, PC + 4 PC, S1 S S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 S S2 A + sign_ext(IR[15-0]) ALUOut, ‘LW’S3 + ‘SW’S5 S S3 M[ ALUOut] MDR, S4 S S4 MDR R[ IR[20-16]], S0 S S5 B M[ ALUOut], S0 S S6 A op B ALUOut, S7 S S7 ALUOut R[IR[15-11]], S0 S S8 Zero PC + Zero ALUOut PC, S0 S S9 PC[31-28] : shlt2(IR[25-0]) PC, S0 S

  22. REGISTER FILE CONTROL R[IR[25-21]] A, R[IR[20-16]] B MDR R[ IR[20-16]], ALUOut R[IR[15-11]], Read Reg 1 Data 1 Read Reg 2 Write Reg Data 2 Write Data

  23. R[IR[25-21]] A, R[IR[20-16]] B MDR R[ IR[20-16]], ALUOut R[IR[15-11]], IR[25-21] Read Reg 1 A Data 1 IR[20-16] Read Reg 2 Write Reg B Data 2 Write Data

  24. R[IR[25-21]] A, R[IR[20-16]] B MDR R[ IR[20-16]], ALUOut R[IR[15-11]], RegWrite IR[25-21] Read Reg 1 A Data 1 IR[20-16] Read Reg 2 0 1 Write Reg B Data 2 IR[15-11] RegDst Write Data ALUOut 0 1 MDR MemtoReg

  25. RegDst MemtoReg RegWrite S1 R[IR[25-21]] A, R[IR[20-16]] B S4 MDR R[ IR[20-16]], S7 ALUOut R[IR[15-11]], RegWrite IR[25-21] Read Reg 1 A Data 1 IR[20-16] Read Reg 2 0 1 Write Reg B Data 2 IR[15-11] RegDst Write Data ALUOut 0 1 MDR MemtoReg

  26. RegDst MemtoReg RegWrite S1 R[IR[25-21]] A, R[IR[20-16]] B x x 0 S4 MDR R[ IR[20-16]], S7 ALUOut R[IR[15-11]], RegWrite IR[25-21] Read Reg 1 A Data 1 IR[20-16] Read Reg 2 0 1 Write Reg B Data 2 IR[15-11] RegDst Write Data ALUOut 0 1 MDR MemtoReg

  27. RegDst MemtoReg RegWrite S1 R[IR[25-21]] A, R[IR[20-16]] B x x 0 S4 MDR R[ IR[20-16]], 0 1 1 S7 ALUOut R[IR[15-11]], RegWrite IR[25-21] Read Reg 1 A Data 1 IR[20-16] Read Reg 2 0 1 Write Reg B Data 2 IR[15-11] RegDst Write Data ALUOut 0 1 MDR MemtoReg

  28. RegDst MemtoReg RegWrite S1 R[IR[25-21]] A, R[IR[20-16]] B x x 0 S4 MDR R[ IR[20-16]], 0 1 1 S7 ALUOut R[IR[15-11]], 1 0 1 RegWrite IR[25-21] Read Reg 1 A Data 1 IR[20-16] Read Reg 2 0 1 Write Reg B Data 2 IR[15-11] RegDst Write Data ALUOut 0 1 MDR MemtoReg

  29. State Register Transfers S0 M[PC] IR, PC + 4 PC, S1 S S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 S S2 A + sign_ext(IR[15-0]) ALUOut, ‘LW’S3 + ‘SW’S5 S S3 M[ ALUOut] MDR, S4 S S4 MDR R[ IR[20-16]], S0 S S5 B M[ ALUOut], S0 S S6 A op B ALUOut, S7 S S7 ALUOut R[IR[15-11]], S0 S S8 Zero PC + Zero ALUOut PC, S0 S S9 PC[31-28] : shlt2(IR[25-0]) PC, S0 S

  30. PC + 4 PC PC + shlt2[sign_ext(IR[15-0])] ALUOut A + sign_ext(IR[15-0]) ALUOut A op B ALUOut Zero PC + Zero ALUOut PC PC Zero ALU ALUOut ALU Control IR[0-5] ALUOp

  31. ALU Control INSTRUCTION OP FUNCT ALUOp ALU Action ALU control add 0 32 10 add 010 subtract 0 34 10 subtract 110 AND 0 36 10 and 000 OR 0 37 10 or 001 set on less than 0 42 10 slt 111 load word 35 na 00 add 010 store word 43 na 00 add 010 branch equal 4 na 01 subtract 110 ALUOp = 10 if the operation depends on the funct field 00 if add 01 if subtract

  32. PC + 4 PC PC + shlt2[sign_ext(IR[15-0])] ALUOut A + sign_ext(IR[15-0]) ALUOut A op B ALUOut Zero PC + Zero ALUOut PC PC Zero ALU ALUOut ALU Control IR[5-0] ALUOp

  33. PC + 4 PC PC + shlt2[sign_ext(IR[15-0])] ALUOut A + sign_ext(IR[15-0]) ALUOut A op B ALUOut Zero PC + Zero ALUOut PC PC PC 0 1 A Zero ALUSrcA ALU ALUOut ALU Control IR[5-0] ALUOp

  34. PC + 4 PC PC + shlt2[sign_ext(IR[15-0])] ALUOut A + sign_ext(IR[15-0]) ALUOut A op B ALUOut Zero PC + Zero ALUOut PC PC PC 0 1 A Zero ALUSrcA ALU B 0 1 2 3 ALUOut 4 sign_ext(IR[15-0]) shlt2 ALU Control ALUSrcB IR[5-0] ALUOp

  35. ALUSrcA ALUSrcB S0 PC + 4 PC S1 PC + shlt2[sign_ext(IR[15-0])] ALUOut S2 A + sign_ext(IR[15-0]) ALUOut S6 A op B ALUOut S8 Zero PC + Zero ALUOut PC PC PC 0 1 A Zero ALUSrcA ALU B 0 1 2 3 ALUOut 4 sign_ext(IR[15-0]) shlt2 ALU Control ALUSrcB IR[5-0] ALUOp

  36. ALUSrcA ALUSrcB S0 PC + 4 PC 0 01 S1 PC + shlt2[sign_ext(IR[15-0])] ALUOut S2 A + sign_ext(IR[15-0]) ALUOut S6 A op B ALUOut S8 Zero PC + Zero ALUOut PC PC PC 0 1 A Zero ALUSrcA ALU B 0 1 2 3 ALUOut 4 sign_ext(IR[15-0]) shlt2 ALU Control ALUSrcB IR[5-0] ALUOp

  37. ALUSrcA ALUSrcB S0 PC + 4 PC 0 01 S1 PC + shlt2[sign_ext(IR[15-0])] ALUOut 0 11 S2 A + sign_ext(IR[15-0]) ALUOut S6 A op B ALUOut S8 Zero PC + Zero ALUOut PC PC PC 0 1 A Zero ALUSrcA ALU B 0 1 2 3 ALUOut 4 sign_ext(IR[15-0]) shlt2 ALU Control ALUSrcB IR[5-0] ALUOp

  38. ALUSrcA ALUSrcB S0 PC + 4 PC 0 01 S1 PC + shlt2[sign_ext(IR[15-0])] ALUOut 0 11 S2 A + sign_ext(IR[15-0]) ALUOut 1 10 S6 A op B ALUOut S8 Zero PC + Zero ALUOut PC PC PC 0 1 A Zero ALUSrcA ALU B 0 1 2 3 ALUOut 4 sign_ext(IR[15-0]) shlt2 ALU Control ALUSrcB IR[5-0] ALUOp

  39. ALUSrcA ALUSrcB S0 PC + 4 PC 0 01 S1 PC + shlt2[sign_ext(IR[15-0])] ALUOut 0 11 S2 A + sign_ext(IR[15-0]) ALUOut 1 10 S6 A op B ALUOut 1 00 S8 Zero PC + Zero ALUOut PC PC PC 0 1 A Zero ALUSrcA ALU B 0 1 2 3 ALUOut 4 sign_ext(IR[15-0]) shlt2 ALU Control ALUSrcB IR[5-0] ALUOp

  40. ALUSrcA ALUSrcB S0 PC + 4 PC 0 01 S1 PC + shlt2[sign_ext(IR[15-0])] ALUOut 0 11 S2 A + sign_ext(IR[15-0]) ALUOut 1 10 S6 A op B ALUOut 1 00 S8 Zero PC + Zero ALUOut PC 1 00 PC PC 0 1 A Zero ALUSrcA ALU B 0 1 2 3 ALUOut 4 sign_ext(IR[15-0]) shlt2 ALU Control ALUSrcB IR[5-0] ALUOp

  41. ALUOp S0 PC + 4 PC 00 add S1 PC + shlt2[sign_ext(IR[15-0])] ALUOut 00 add S2 A + sign_ext(IR[15-0]) ALUOut 00 add S6 A op B ALUOut 10 funct S8 Zero PC + Zero ALUOut PC 01 sub PC PC 0 1 A Zero ALUSrcA ALU B 0 1 2 3 ALUOut 4 sign_ext(IR[15-0]) shlt2 ALU Control ALUSrcB IR[5-0] ALUOp

  42. State Register Transfers S0 M[PC] IR, PC + 4 PC, S1 S S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 S S2 A + sign_ext(IR[15-0]) ALUOut, ‘LW’S3 + ‘SW’S5 S S3 M[ ALUOut] MDR, S4 S S4 MDR R[ IR[20-16]], S0 S S5 B M[ ALUOut], S0 S S6 A op B ALUOut, S7 S S7 ALUOut R[IR[15-11]], S0 S S8 Zero PC + Zero ALUOut PC, S0 S S9 PC[31-28] : shlt2(IR[25-0]) PC, S0 S

  43. PC + 4 PC Zero PC + Zero ALUOut PC PC[31-28] : shlt2(IR[25-0]) PC PC PCWrite + PCWriteCond * Zero

  44. PC + 4 PC Zero PC + Zero ALUOut PC PC[31-28] : shlt2(IR[25-0]) PC ALU Result 0 1 2 PC PCWrite + PCWriteCond * Zero PCSource

  45. PC + 4 PC Zero PC + Zero ALUOut PC PC[31-28] : shlt2(IR[25-0]) PC ALU Result 0 1 2 ALUOut PC PCWrite + PCWriteCond * Zero PCSource

  46. PC + 4 PC Zero PC + Zero ALUOut PC PC[31-28] : shlt2(IR[25-0]) PC ALU Result 0 1 2 ALUOut PC PC[31-28] : shlt2(IR[25-0]) PCWrite + PCWriteCond * Zero PCSource

  47. PCSource PCWrite PCWriteCond S0 PC + 4 PC S8 Zero PC + Zero ALUOut PC S9 PC[31-28] : shlt2(IR[25-0]) PC ALU Result 0 1 2 ALUOut PC PC[31-28] : shlt2(IR[25-0]) PCWrite + PCWriteCond * Zero PCSource

  48. PCSource PCWrite PCWriteCond S0 PC + 4 PC 00 1 x S8 Zero PC + Zero ALUOut PC S9 PC[31-28] : shlt2(IR[25-0]) PC ALU Result 0 1 2 ALUOut PC PC[31-28] : shlt2(IR[25-0]) PCWrite + PCWriteCond * Zero PCSource

  49. PCSource PCWrite PCWriteCond S0 PC + 4 PC 00 1 x S8 Zero PC + Zero ALUOut PC 01 0 1 S9 PC[31-28] : shlt2(IR[25-0]) PC ALU Result 0 1 2 ALUOut PC PC[31-28] : shlt2(IR[25-0]) PCWrite + PCWriteCond * Zero PCSource

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