ADC & DAC:

1. ADC & DAC: Most of the physical quantities such as temperature, pressure, displacement,vibration etc exist in analog form. But it is difficult to process, store or transmit the analog signal because errors get introduced easily. Hence to enable these signals to be processed digitally, these are to be represented in equivalent digital form. Hence the need for ADC. Again, after processing is over, the digital signals are to be converted into equivalent analog signals for human observations or activation of further circuits. For this, we need DAC.

2. D TO A CONVERTERS Vo= output voltage VFS = full scale output voltage K - scaling factor usually adjusted to unity d1d2... Dn = n-bit binary fractional word with the decimal point located at the left d1- most significant bit (MSB) with a weight of VFS/2 dn - least significant bit (LSB) with a weight of VFS/2n

3. Current to Voltage Converter Binary Weighed Resistors Figure 9-18 (a) D/A converter with binary-weighted resistors, (b) Decimal equivalent of binary inputs Gayakwad.

4. The current through RF depends on switch position IF is 0.5,1, 1.5, 2, 2.5 mA etc. Vo=IFxRF. Since RF is 1K, the VO = 0.5,1,1.5V…etc.

5. The important points to note down are When all the input bits are’0’, What is the minimum output Vo.? Resolution = ± ½ LSB. When all the input bits are ‘1’ What is the output Vo.? Maximum VO. What is the speed of conversion?

6. Specifications of DAC • Resolution For an n bit INPUT, the total number of steps is 2n-1, Then % resolution x100 is defined as the ratio of a change in output voltage resulting from a change of 1 LSB at the digital inputs. VoFS = Full-scale output Voltage. Example: For an 8bit DAC, if full scale output voltage is 10.2V, what is the resolution? R= = 40mV/LSB. 1 LSB change results in 40mV output.

7. Accuracy. Accuracy = ½ LSB. In the above example it is 20mV. Problem: If n=4; VoFS = 15V; R = 15/(24-1) = 1V/LSB. What is Vout for an input of 0110? Vo = Resolution x D. D=Decimal Equivalent D= (0110)2 = 6 Vo = (1V/LSB) x 6 = 6V.

8. DAC SPECIFICATIONS • Resolution: (2n -1) Total No. of Steps. % Resolution = x 100 • Linearity. Relation between input & output. • Accuracy: Expressed as fraction of LSB • Settling time. Time required for the O/P of DAC to settle to with in ½ LSB of the final value for a given digital input. • Speed of conversion. Conversion Time. • Supply Rejection: • The ability of DAC to maintain accuracy and linearity when the supply voltage changes.

9. Types of DAC 1.Binary weighted DAC 2.R-2R ladder type DAC

10. BINARY WEIGHTED DAC Single VR is used. n binary weighed currents, i1,i2,i3 etc. -VR Multiple values of resistors 2R, 4R, 8R etc are used Binary weighed currents, I1, I2, I3 are used.

11. IT = I1+I2+I3+ +In The output voltage is the voltage across Rf and it is given as When RF = R, Vo is given as

12. LIMITATIONS OF BINARY WEIGHTED RESISTORS • As the resolution increases, the resistor value increases. • Difficult to fabricate on chip. For an 8 bit DAC the largest resistor is 128 times the smallest one. • Theaccuracy is low, since depends on resistor values.

13. If VR ia – ve, we get +ve stepped voltage as shown.

14. Ladder Type Voltage-Switched R-2R DAC voltage scaling is used -VR Only TWO values of resistors R MSB LSB 0 0 0 1 Fig.11.8 Four Bit R/2R Ladder D/A Converter Let b1b2b3b4 1000 Only TWO values of resistors are required. Identical resistors and voltage scaling is used unlike binary weighed DAC binary weighed currents are used.

15. R-2R LADDER TYPE D/A CONVERTER. 0 0 1 0 2 ║el

16. (R+R) ║ 2R +

17. V0 = -VR/2 = VR/2 Equv. Of 3rd stage. V0 = -VR/2 For b1,b2,b3,b4 = 1000, output Vo= VR/2 0100, VR/4, 0010, VR/8,0001, VR/16 For n bit DAC

18. In the previous example when the binary no. is 1000, V0 = -VR/2, if RF=R, & n=4 V0 = VR/2

19. Ladder Type Voltage-Switched R-2R DAC voltage scaling is used -VR Only TWO values of resistors -VR/2 R MSB LSB 0 0 0 1 Fig.11.8 Four Bit R/2R Ladder D/A Converter Let b1b2b3b4 1000 Vo = (-Rf/R) (-VR/2) If Rf = R, Vo = (VR/2)

20. VR/20 VR/21 VR/22 VR/2n Inverted or Current Mode R-2R Ladder D/A Converter. MSB & LSB are interchanged.

21. Since both the positions of switches are at ground potential, the current flowing through resistances is constant and it is independent of switch position. These currents can be given as

22. When Rf = R, Vo is given as

23. R-2R LADDER TYPE DAC • Uses only two values of resistors • Overcomes the limitations of Binary weighted DAC • OPAMP is connected in inverting mode • Each digital input is applied through R-2R network and Vref

24. Sources of Errors in DAC • Linearity Error • The error is defined as the amount by which the actual output differs from the ideal straight-line output. • Fig. 8.19 shows the linearity error in the transfer characteristics of DAC. It is mainly due to the errors in the current source resistor values. Fig. 8.19 Linearity error in transfer characteristics of DAC

25. Offset Error • The offset error is defined as the nonzero level of the output voltage when all inputs are zero. • It adds a constant value to all output values, as shown in Fig. 8.20. • It is due to the presence of offset voltage in op-amp and leakage currents in the current switches. Fig. 8.20 Offset error in transfer characteristics of DAC Gain Error It is defined as the difference between the calculated gain of the current to voltage converter and the actual gain achieved. It is due to the errors in the feedback resistor on the current to voltage converter op-amp. Fig. 8.21 Gain error in transfercharacteristics of DAC.

26. Quantization Error This is Caused in ADC.For a given binary output, the exact analog input is uncertain. This is because the binary output increases linearly in steps.

27. IC 1408 D/A Converter (DAC0800, DAC0808 are exact pin to pin equivalents.) The 1408 is an 8 bit R/2R ladder type D/A converter compatible with TTL and CMOS logic. It is designed to use where the output current is linear product of an eight bit digital word. The IC 1408 consists of a reference current amplifier, an R/2R ladderand eight high speed current switches. It has eight input data lines A1 (MSB) through A8 (LSB). It requires 2 mA reference current for full scale input and two power supplies Vcc = + 5 V and VEE = - 15 V (VEE can range from 5 V to - 15 V). The voltage Vref and resistor R14 determines the total reference current source and R15 is generally equal to R14 to match the input impedance of the reference current amplifier.

28. Important Electrical Characteristics for IC 1408 Reference current : 2 mA Supply voltage : + 5 Vcc and - 15 V VEE Setting time : 300 ns Full scale output current : 1.992 mA Accuracy : 0.19 % When input = 11111111, Io is given by V0= 1.992mA x 5KΩ=9.961V

29. Unipolar Note : The arrow on the pin 4 shows the output current direction. It is inward. This means that IC 1408 sinks current. At (0000 0000) 2binary input it sinks zero current and at(11111111)2binary input itsinks 1.992 mA. This circuit can be modified to give bipolar output.

30. Bipolar

31. Condition 1 : For binary input (00H) When binary input is 00H, the output current Io at pin 4 is zero. Due to this current flowing through RB (1 mA) flows through Rf giving Vo = - 5 V. Condition 2 : For binary input 80H (10000000) When binary input is 80H, the output current Io at pin 4 is 1 mA. By applying KCL at node A we get, -Ib+I0+If = 0. Substituting values of IB and Io we get, -(1 mA) + (1 mA) + If = 0: If = 0 and therefore Vo = 0V. Condition 3 : For binary input FFH (11111111) When binary input is FFH, the output current I0at pin 4 is 2 mA. By applying KCL at node A we get, -IB+Io+If = 0 substituting values of IB and Io we get, - (1 mA) + (2 mA) + If = 0 If = - 1 mA Therefore, Vo = + 5 V. In this way, circuit shown in the Fig. 9.26 gives output in the bipolar range.

32. Example: For above bi-polar circuit, calculate the output voltage, V0 for digital input word of • 00000000 • 01111111 • 10000000 • 11111111 Current for 1 LSB is 8µA. IFS = 8µAx255=2.04mA. For 00000000 input, I0 = 8µA x 0 = 0 I0=2.040mA-0=2.04mA. V0= (0-2.04mA)(5KΩ) = -10.20V

34. ADC’s • Converts analog signal into digital data • Used in Data acquisition systems & Digital instruments etc

35. TYPES OF ADC • Successive approximation ADC • Parallel converter or Flash type ADC • Ramp Converter. • Dual Slope Converter.

36. Fig. 8.26 Analog input Vs Digital output Resolution Fig. 8.26 shows eight (23) discrete output states from 000 to 111, each step being 1/8 V apart. Therefore, we can say that expression of ADC resolution is resolution = 1/2n (1) In the above case n=3 Resolution is also defined as the ratio of a change in value of input voltage, X, needed to change the digital output by 1 LSB. If the full scale input voltage required to cause a digital output of all l's is Vifs, then Resolution = ViFS/2n (2)

37. If viFs is the maximum input voltage, which will cause all 1’s at the output. ViFs = VFs -1LSB Example: For an input voltage of 0-10V, what is the resolution? 1LSB = 10V/28= 39.1mV What is the input voltage that generates all 1’s at output? 10V-39.1mV = 9.961V. What is the digital output for an input voltage of 4.8V? D= 4.8/39.1 = 122.76 say 123. The binary value is 01111011

38. Quantization Error Fig. 8.26 shows that the binary output is 001 for all values of Vi between 1/4 and ½ V. There is an unavoidable uncertainty about the exact value of Viwhen the output is 001. This uncertainty is specified as quantization error. Its value is  ½ LSB. It is given as, QE = (3) Increasing the number of bits results in a finer resolution and a smaller quantization error. Conversion Time It is an important parameter for ADC. It is defined as the total time required to convert an analog signal into its digital output. It depends on the conversion technique used and the propagation delay of circuit components.

39. SUCCESSIVE APPROXIMATION ADC • Widely used • Similar to Counter type ADC except that ,a SAR is used • SAR acts as programmable Up/Down counter • Completion of conversion , triggered by a change in the state of the comparator • Much faster than the counter type

40. SUCCESSIVE APPROXIMATION ADC

41. Implements Binary search algorithm • Initially, DAC input set to midscale (MSB =1) • VIN > VDAC , MSB remains 1. Next bit is set to 1 • VIN < VDAC , MSB set to 0. Next bit is set to 1 • MSB’s remain same after each conversion and next 3 bits are processed. Then next 2 bits, first 2 remaining same etc. • Algorithm is repeated until LSB. • DAC [input] = ADC [output] • N cycles required for N-bit Conversion. Typical accuracy levels of 8 to 12 bits.

42. 4 3 Upper arrow 1 2 Lower arrow 0 Vin> 11 1 Next bit is always changed to ‘1’ 2nd Bit 3rd Bit 4th Bit First Bit 0 Vin<01 0 • Start conversion pulse will set all zeros in SAR. • MSB is set to 1 and others remaining 0’s (1/2 the input voltage). DAC output is compared with unknown voltage. (1000) • If unknown voltage is higher, the bit under comparison is retained1 and the next bit is made 1. • If unknown voltage isless, the bit under comparison is made 0 and the next bit is made 1. • MSB’s remain same after each conversion and next 3 bits are processed. Then next 2 bits, first 2 remaining same etc. • Then comparison moves to next bit and process continues till last bit.

43. For 8 bit Successive Approximation, only 8 cycles are required irrespective of the amplitude of analog input voltage. Ex: For 8 bit SA, A/D, if 2MHz clock is used, what is the conversion time? Ans: 1/2MHz = 0.5µs. Total time required for conversion = Time required for resetting SAR + Conversion time i.e. (8+1) 9 clock cycles = 9x0.5µs = 4.5µs

44. Ramp or Single Slope Integrating ADC • Slow but accurate • Doesn't use a DAC. Single slope integrating ADC: • Feed the input signal into an integrator Vinteg ≈ Vin Vinteg integrator comparator • Connect the comparator output to a counter through a gate which counts the number of clock cycles needed to reach Vref • Reset the clock, discharge the capacitor and repeat.

45. When the ramp generator is first turned on, several things happen. • 1. The gate is turned on from it’s previously off state. • 2. Clock pulses from the clock generator are allowed through the gate to the counter. • 3. The counter then starts to count each clock pulse as it arrives. • During the time the ramp voltage is rising there is a relatively stable state in the circuit.

46. 4. Once the ramp voltage reaches the value of Vin, the gate to turn off. In doing so the gate prevents any further clock pulses from reaching the counter. The major disadvantage of this system 1. Very stable clock signal is required. 2. Noise in the signal causes errors. 3. Input Filters are required. 4. Stability is poor.

47. Once the ramp voltage reaches the value of Vin, the gate to turn off. In doing so the gate prevents any further clock pulses from reaching the counter. AND When Vin = Vramp gate is closed and counting stops. Single Slope Integration ADC

48. Fig. 8.28.

49. The main limitations of this circuit are: • Its resolution is less. Hence for applications which require resolution of 9 part in 20,000 or more, this ADC is not stable. • Variations in ramp generator due to time, temperature or input voltage sensitivity also cause a lot of problems. • Big problem with single slope integration is calibration drift • The counting rate of the counter and the voltage slope of • the integrator must always match each other exactly. • This puts a severe requirement on the stability and • accuracy of the integrator (and also the comparator).

50. Dual Slope Integrating ADC T1 A "cycle clock" generates a pulse of fixed length T1 during which the input voltage is allowed to charge the integrator. After T1 integrator discharges through a reference voltage of opposite polarity. When the integrator voltage returns to zero, comparator flips and disables NAND gate. Counter stops counting and is read out is displayed.