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Status of SPECS

Status of SPECS. SPECS-SLAVE architecture I2C implementation JTAG implementation Parallel bus SPECS-SLAVE board JTAG/I2C development schedule. S pecs-Slave chip. PBA [3:0]. (Partial. Broadcast Address. ). Reset*. Slave. Address. [7:0]. 40. MHz Clk. CTRL. Data [7:0]. Subadd.

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Status of SPECS

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  1. Status of SPECS SPECS-SLAVE architecture I2C implementation JTAG implementation Parallel bus SPECS-SLAVE board JTAG/I2C development schedule

  2. Specs-Slave chip PBA [3:0] (Partial Broadcast Address ) Reset* Slave Address [7:0] 40 MHz Clk CTRL Data [7:0] Subadd [7:0] Read* SDA_MS Write * SCL_MS SPECS Parallel Bus SPECS Bus User Interrupt Local slave bus FIFOempty * SPECS SDA_SM ChipSelect * [7:0] SCL_SM NTA [15:0] [3:0] Byte number JTAG I2C S CLreturn TDO TCK SDA Bus_CS[7:0] SDA return SCL TMS TDI JTAG I2C • Compoment • SX- A32 • + PQ208 package • - All I/Os fixed at the same voltage • AX-125 • + n I/O Banks for different voltages • + new familly from ACTEL • + internal ressources • - BGA packages (FG 256) • - Bigger what we need

  3. Architecture of SPECS slave FPGA

  4. SCL SDA I2C inter- face SCL SPECS slave board Chip detector OC SDA On detector Remoteboard I2C Hardware Implementation

  5. I2C SPECS Characteristics • Characteristics • 7bit addressing capability • No capability for handshake resynchronisation • Bandwidth 1Mb/s • Transfer rate 45kByte/s for one Byte access • Maximun transfer rate 122kByte/s for 31Byte data frame • I2C Acknowledgement locally managed by SPECS-SLAVE

  6. 1 bit= 100 ns 1 bit= 100 ns data[0:7] data[0:7] LSb LSb MSb MSb TDI TDI TMS TMS TRst TRst TCK=1 TCK=0 JTAG output JTAG bus register TDI Half word JTAG inter- face On detector Remote board TMS SPECS slave board TCK TDO JTAG Hardware Implementation • Characteristics • bandwidth 1Mb/s • 122kByte/s • for 31Byte frame

  7. SPECS Slave board Front panel RJ45 SPECS connector MS_S DA I2C Bus JT AG or I2C RJ45 DIFFERENTIAL MS_SCL JTAG Bus LINK BACKPLANE CONNECTOR SPECS + TTC SM_S DA RJ45 En/dir SPECS en/dir[15] 2 SM - SCL SLAVE RJ45 Actel RJ45 en/dir[0] 54SX?? JTAG or I2C Bus 8 BUSSES RJ45 RJ45 RJ45 JT AG or I2C SPECS RJ45 DIFFERENTIAL SLAVE LINK BOARD En/dir

  8. PCI SPECS Prototype Master Board Firmware version 2.0 beta JTAG LVDS bus LVDS drivers 2 SPECS Masters + 1 SPECS Slave APEX 20K100E PQFP 240 RJ45 LVDS drivers I2C LVDS bus RJ45 SPECS bus PLX local bus SPECS LVDS bus LVDS drivers PCI target interface PLX 9030 PQFP 176 RJ45 LVDS drivers RJ45 PCI SPECSmaster PCI bus PCI connector PC mother board

  9. Status of Specs firmware version 1 • FIRMWARE Development in Verilog language and synthesis with SYNPLIFY • Slave • SPECS_SLAVE targeted on APEX : receiver, parallel interface, I2C curently under test. • Routing (20% of the logic cells in an APEX 20K100 or 34% of the logic cells in a SX32-A) including parallel interface and I2C interface. • Master • SPECS_MASTER targeted on APEX : SPECS transfer, PLX bus interface currently under test. • Routing (28% of the logic cells in an APEX 20K100 and 61 % of the ESBs) including 2 FIFOs of256x32b.

  10. Status of PCI board version 2.0 • HARDWARE: • PLX9030 • Internal register access and reconfiguration of PLX’s configuration EEprom have been tested. • Local bus access in ‘target single read/write’ PCI mode to the SPECS Master has been tested. • Master board : LVDS output no tested. • SOFTWARE • WINDOWS NT • PCI driver delivered by PLX(SDK-PRO). Tested in ‘target single read/write’ but not in burst mode. • Windows interface (PLXMON) has been use to access and configure PLX. • SPECS master-board & SPECS slave libraries developped in C code. • LINUX • Linux driver delivered by PLX (SDK-PRO). Not yet tested.

  11. Schedule for the SPECS system February March April May June July Firmware version 2.0 Beta PCI Master board vesrsion 1 Firmware version 2.0 Windows Software PCI Master board version 2 Linux Software Version 2.1 Documentation SPECS-Slave board

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