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3DIC and I/O redistribution RAL/Uppsala

3DIC and I/O redistribution RAL/Uppsala. Paul Seller Richard Brenner. 3DIC with EMFT. 3DIC with EMFT. A lot of detailed work has been done to prepare TSV cut technology and to prepare masks for AMS process including Oxide/Nitride steps for metal coverage.

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3DIC and I/O redistribution RAL/Uppsala

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  1. 3DIC and I/O redistributionRAL/Uppsala Paul Seller Richard Brenner Paul Seller

  2. 3DIC with EMFT Paul Seller

  3. 3DIC with EMFT A lot of detailed work has been done to prepare TSV cut technology and to prepare masks for AMS process including Oxide/Nitride steps for metal coverage. 4 top analogue wafers will be complete end of June One diced and sent to RAL to test if analogue chip still working. Also there is contact chain for testing. SLID deposition on 3 bottom and 3 top wafers finished in Aug. Bonded wafers ready in Oct/Nov for dicing and testing. Test system ready in Oct/Nov and start transferring to Uppsala for batch testing of devices in 2013. Paul Seller

  4. 3DIC with EMFT Diamond pad is the bond pad to the CZT detector. The other pad is the connection out of the pixel and this connects to the four 11x4um TSVs This is without the protection trench. (with trench on left). Paul Seller

  5. I/O redistribution Paul Seller

  6. I/O redistribution Conventional Hexitec 3-side device. 150 um gaps but large dead region on 4th side. ASIC gold stud bonded to 3mm CZT and wire bonded to PCB Paul Seller

  7. I/O redistribution Redistribution test device with wire bonding on back of 120um thin ASIC. After laser cutting of outer bonds fully working. Paul Seller

  8. CZT Detector TSV ASIC Door-step with connector I/O redistribution Next ASIC will reduce all the readout circuitry. Geometry for 4-side butting and no dead region Paul Seller

  9. I/O redistribution Plan Small readout area ASIC designed for submission Nov 2012 Probe test ASIC March 2013 TSV redistribution and test with back side wire bonding June 2013 Paul Seller

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