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Computer Organization Chapter 2 Instructions: Language of the Computer

Computer Organization Chapter 2 Instructions: Language of the Computer. Instructions:. Language of the Machine More primitive than higher level languages e.g., no sophisticated control flow Very restrictive e.g., MIPS Arithmetic Instructions

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Computer Organization Chapter 2 Instructions: Language of the Computer

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  1. Computer OrganizationChapter 2Instructions: Language of the Computer

  2. Instructions: • Language of the Machine • More primitive than higher level languages e.g., no sophisticated control flow • Very restrictive e.g., MIPS Arithmetic Instructions • We’ll be working with the MIPS instruction set architecture • similar to other architectures developed since the 1980's • used by NEC, Nintendo, Silicon Graphics, Sony Design goals: maximize performance and minimize cost, reduce design time

  3. MIPS arithmetic • All instructions have 3 operands • Operand order is fixed (destination first)Example: C code: a = b + c MIPS ‘code’: add a, b, c (we’ll talk about registers in a bit)“The natural number of operands for an operation like addition is three…requiring every instruction to have exactly three operands, no more and no less, conforms to the philosophy of keeping the hardware simple”

  4. MIPS arithmetic • Design Principle: simplicity favors regularity • Of course this complicates some things... C code: a = b + c + d; MIPS code: add a, b, c add a, a, d • Operands must be registers, only 32 registers provided • Each register contains 32 bits • Design Principle: smaller is faster - Why?

  5. Control Input Memory Datapath Output Processor I/O Registers vs. Memory • Compiler associates variables with registers • What about programs with lots of variables (some on stack)

  6. Processor Memory Stored Program Concept • Instructions are bits • Programs are stored in memory — to be read or written just like data • Fetch & execute cycle • fetch • decode • execute memory for data, programs, compilers, editors, etc.

  7. Memory Organization • Viewed as a large, single-dimension array, with an address • A memory address is an index into the array • "Byte addressing" means that the index points to a byte of memory • Address – stored on 32 bits => can label 232 bytes in mem. => max RAM 4GB 0 8 bits of data 1 8 bits of data 2 8 bits of data 3 8 bits of data 4 8 bits of data 5 8 bits of data 6 8 bits of data ...

  8. Memory Organization • Bytes are nice, but most data items use larger "words" • For MIPS, a word is 32 bits or 4 bytes • 232 bytes with byte addresses from 0 to 232-1 • 230 words with byte addresses 0, 4, 8, ... 232-4 • Words are aligned i.e., what are the least 2 significant bits of a word address? 0 32 bits of data 4 32 bits of data Registers hold 32 bits of data 8 32 bits of data 12 32 bits of data ...

  9. Instructions • Load and store instructions • Example: C code: A[12] = h + A[8];Note: $s2 holds var. h $s3 holds starting addr. for array A MIPS code: lw $t0, 32($s3) add $t0, $s2, $t0 sw $t0, 48($s3) • Can refer to registers by name (e.g., $s2, $t0) instead of number • Store word specifies destination register last • Remember arithmetic operands are registers, not memory! Can’t write: add 48($s3), $s2, 32($s3)

  10. Memory . . . 0001 1000 + . . . 1001 0100 . . . 1010 1100 = 0x120040ac 2410 + $s2 = 0xf f f f f f f f 0x120040ac $t0 0x12004094 $s2 op rs rt 16 bit offset 0x0000000c 0x00000008 0x00000004 0x00000000 data word address (hex) Machine Language - Load Instruction • Load/Store Instruction Format (I format): lw $t0, 24($s2)

  11. So far we’ve learned: • MIPS — loading words but addressing bytes — arithmetic on registers only • InstructionMeaningadd $s1, $s2, $s3 $s1 = $s2 + $s3sub $s1, $s2, $s3 $s1 = $s2 – $s3lw $s1, 100($s2) $s1 = Memory[$s2+100] sw $s1, 100($s2) Memory[$s2+100] = $s1

  12. Machine Language • Instructions, like registers and words of data, are also 32 bits long • Example: add $t0, $s1, $s2 • registers have numbers, $t0=8, $s1=17, $s2=18 • Instruction Format (R-format):000000 10001 10010 01000 00000 100000 op rs rt rd shamt funct • Can you guess what the field names stand for?

  13. Machine Language • Consider the load-word and store-word instructions, • What would the regularity principle have us do? • New principle: Good design demands a compromise • Introduce a new type of instruction format • I-type for data transfer instructions • other format was R-type for register • Example: lw $t0, 32($s2) 35 18 8 32 op rs rt 16 bit number • Where's the compromise?

  14. MIPS Registers - Policy of Use Conventions

  15. op rs rt rd shamt funct op rs rt 16 bit address op 26 bit address Instruction Formats and Examples: • InstructionMeaningadd $s1,$s2,$s3 $s1 = $s2 + $s3sub $s1,$s2,$s3 $s1 = $s2 – $s3lw $s1,100($s2) $s1 = Memory[$s2+100] sw $s1,100($s2) Memory[$s2+100] = $s1bne $s4,$s5,L Next instr. is at Label if $s4 != $s5beq $s4,$s5,L Next instr. is at Label if $s4 = $s5j Label Next instr. is at Label • Formats: R I J

  16. Control – Conditional Branch • Decision making instructions • alter the control flow • i.e., change the "next" instruction to be executed • MIPS conditional branch instructions:bne $t0, $t1, Label beq $t0, $t1, Label • I instruction format • Example: if (i==j) h = i + j;bne $s0, $s1, Label add $s3, $s0, $s1 Label: ....

  17. More Branch Instructions • We have beq, bne, but what about other kinds of branches (e.g., branch-if-less-than)? For this, we need yet another instruction, slt • Set on less than instruction slt $t0, $s0, $s1 # if $s0 < $s1 then # $t0 = 1 else # $t0 = 0 • Can use slt, beq, bne, and the fixed value of 0 in register $zero to create other conditions • less than blt $s1, $s2, Label • less than or equal to ble $s1, $s2, Label • greater than bgt $s1, $s2, Label • great than or equal to bge $s1, $s2, Label • Such branches are included in the instruction set as pseudo instructions - recognized (and expanded) by the assembler • Its why the assembler needs a reserved register ($at) slt $at, $s1, $s2 #$at set to 1 if bne $at, $zero, Label #$s1 < $s2 2

  18. op 26-bit address Control – Unconditional Branch • MIPS unconditional branch instructions: j label • instruction format • Example:if (i!=j) beq $s4, $s5, Lab1 h=i+j; add $s3, $s4, $s5 else j Lab2 h=i-j; Lab1: sub $s3, $s4, $s5 Lab2: ... • Can you build a simple for loop?

  19. Addresses in Branches • Instructions: bne $t4,$t5,LabelNext instruction is at Label if $t4  $t5 beq $t4,$t5,LabelNext instruction is at Label if $t4=$t5 • Formats: • Could specify a register (like lw and sw) and add it to 16 bit address • use Instruction Address Register (PC = program counter) • PC contains address of current instr. • its use is automatically implied by instruction • MIPS - PC gets updated (PC+4) during the fetch cycle so that it holds the address of the next instruction • limits the branch distance to -215 to +215-1 instructions from the branch instruction • most branches are local (principle of locality) • What if the branch destination is further away than can be captured in 16 bits? • The assembler comes to the rescue – it inserts an unconditional jump to the branch target and inverts the condition beq $s0, $s1, L1 becomes bne $s0, $s1, L2 j L1 L2: op rs rt 16 bit address I

  20. Instructions for Accessing Procedures • MIPS procedure call instruction:jal ProcedureAddress #jump and link • $a0-$a3 - pass parameters; $v0-$v1 – returned values • Saves PC+4 in register $ra to have a link to the next instruction for the procedure return • Machine format (J format): • Then can do procedure return with a jr $ra #return at $ra address • Instruction format (R format): op 26 bit address op rs funct

  21. high addr top of stack $sp low addr Spilling Registers • What if the callee needs more registers? What if the procedure is recursive? • uses a stack in memory for passing additional values or saving (recursive) return address(es) • One of the general registers, $sp, is used to address the stack (which “grows” from high address to low address) • add data onto the stack – push • $sp = $sp – 4 • data on stack at new $sp • remove data from the stack – pop • data from stack at $sp • $sp = $sp + 4

  22. Example Stack Use int example(int g, int, h, int i, int j) { int f; f = (g + h) -( i + j); return f;} Caller loads argument registers with parameters and performs jal example a0:g, a1:h, a2:i, a3:j, s0:f, t0 and t1 used for exp. evaluation example: addi $sp, $sp, -12 sw $t1, 8($sp) sw $t0, 4($sp) sw $s0, 0($sp) add $t0, $a0, $a1 add $t1, $a2, $a3 sub $s0, $t0, $t1 add $v0, $s0, $zero lw $s0, 0($sp) lw $t0, 4($sp) lw $t1, 8($sp) addi $sp, $sp, 12 jr $ra • Note that temp. registers are typically NOT saved by callee but by caller (pg. A-25) • Caller (e.g. main) • Push a0-a3 • Push t0-t9 • Load args in a0-a3 • Save ret. address in $ra • Callee (e.g. example) • Push ra • Push s0-s7

  23. Logical Operations • sll, srl, and, andi, or, ori, nor sll $t0, $s0, 4 #reg $t2 = reg $s0 << 4 bits • OBS. • the empty bits filled with 0 • rs unused • left shift by i bits = multiply by 2i 0 0 16 10 4 0 op rs rt rd shamt 0

  24. I format op rs rt 16 bit immediate MIPS Immediate Instructions - Constants • Small constants are used often in typical code A = A + 5 • Possible approaches? • put “typical constants” in memory and load them • create hard-wired registers (like $zero) for constants like 1 • have special instructions that contain constants ! addi $sp, $sp, 4 #$sp = $sp + 4 slti $t0, $s2, 15 #$t0 = 1 if $s2<15 • Machine format (I format): • The constant is kept inside the instruction itself! • Immediate format limits values to the range +215–1 to -215

  25. filled with zeros 1010101010101010 0000000000000000 1010101010101010 1010101010101010 How about larger constants? • We'd like to be able to load a 32 bit constant into a register • Access memory – expensive • Better use two immediat instr. to load a 32 bit constant rather than lw • Must use two instructions, new "load upper immediate" instruction lui $t0, 1010101010101010 • Then must get the lower order bits right, i.e.,ori $t0, $t0, 1010101010101010 1010101010101010 0000000000000000 0000000000000000 1010101010101010 ori

  26. Assembly Language vs. Machine Language • Assembly provides convenient symbolic representation • much easier than writing down numbers • e.g., destination first • Machine language is the underlying reality • e.g., destination is no longer first • Assembly can provide 'pseudoinstructions' • e.g., “move $t0, $t1” exists only in Assembly • would be implemented using “add $t0,$t1,$zero” • When considering performance you should count real instructions

  27. Overview of MIPS • simple instructions all 32 bits wide • very structured, no unnecessary baggage • only three instruction formats • OBS. - j and jal (both are J format) use “word address” instead of byte address to jump 4 times further e.g. J 2000 # 2000 is word address # so, jump at 8000 (byte address) op rs rt rd shamt funct R I J op rs rt 16 bit address op 26 bit address

  28. Overview of MIPS

  29. MIPS: Software conventions for Registers 0 zero constant 0 1 at reserved for assembler 2 v0 expression evaluation & 3 v1 function results 4 a0arguments 5 a1 6 a2 7 a3 8 t0temporary: caller saves . . . (callee can clobber) 15 t7 16 s0callee saves . . . (caller can clobber) 23 s7 24 t8temporary (cont’d) 25 t9 26 k0 reserved for OS kernel 27 k1 28 gp Pointer to global area 29 sp Stack pointer 30 fp frame pointer 31 ra Return Address (HW)

  30. op rs rt rd funct Register word operand op rs rt offset Memory word or byte operand base register op rs rt operand Overview of MIPS Operand Addressing Modes • (R) Registeraddressing – operand is in a register • (I) Base (displacement)addressing – operand is at the memory location whose address is the sum of a register and a 16-bit constant contained within the instruction • Register relative (indirect) with 0($a0) • Pseudo-direct with addr($zero) • (I) Immediate addressing – operand is a 16-bit constant contained within the instruction +

  31. op rs rt offset Memory branch destination instruction Program Counter (PC) Memory op jump address | jump destination instruction Program Counter (PC) Overview of MIPS Instruction Addressing Modes • (I) PC-relative addressing – instruction address is the sum of the PC and a 16-bit constant contained within the instruction • (J) Pseudo-direct addressing – instruction address is the 26-bit constant contained within the instruction concatenated with the upper 4 bits of the PC +

  32. MIPS (RISC) Design Principles • Simplicity favors regularity • fixed size instructions – 32-bits • small number of instruction formats • opcode always the first 6 bits • Good design demands good compromises • three instruction formats • Smaller is faster • limited instruction set • limited number of registers in register file • limited number of addressing modes • Make the common case fast • arithmetic operands from the register file (load-store machine) • allow instructions to contain immediate operands

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