EMT243/251 Dr. Rozana Aina Maulat Osman School Microelectronics , Universiti Malaysia Perlis.

1. WEEK 13-14 MOS TRANSISTOR THEORY EMT243/251 Dr. Rozana Aina Maulat Osman School Microelectronics , Universiti Malaysia Perlis.

2. Outline • Characteristic • MOS • Accumulation, Depletion and Inversion • MOSFET (PMOS & NMOS) • I-V ( Linear, Saturation and Cutoff) • DC Transfer Characteristic • CMOS INVERTER • Noise Margin • Pass –Transistor • Switch Level RC Delay

3. PART 1: C-V MOS

4. MOS (Metal-Oxide-Semiconductor) Assume work function of metal and semiconductor are same.

5. MOS materials

6. MOS structure • Shown is the semiconductor substrate with a thin oxide layer and a top metal contact, also referred to as the gate. • A second metal layer forms an Ohmic contact to the back of the semiconductor, also referred to as the bulk. • The structure shown has a p-type substrate. • We will refer to this as an n-type MOS capacitor since the inversion layer contains electrons.

7. Structure and principle of operation • To understand the different bias modes of an MOS we consider 3 different bias voltages. • (1) below the flatband voltage, VFB • (2) between the flatband voltage and the threshold voltage, VT, and • (3) larger than the threshold voltage. • These bias regimes are called the accumulation, depletion and inversion mode of operation.

8. Structure and principle of operation • Charges in a MOS structure under accumulation, depletion and inversion conditions

9. Accumulation, depletion and Inversion

10. Four modes of MOS operation • The four modes of operation of an MOS structure: • Flatband, • Depletion, • Inversion and • Accumulation. • Flatband conditions exist when no charge is present in the semiconductor so that the Si energy band is flat. • Surface depletion occurs when the holes in the substrate are pushed away by a positive gate voltage. • A more positive voltage also attracts electrons (the minority carriers) to the surface, which form the so-called inversion layer. • Under negative gate bias, one attracts holes from the p-type substrate to the surface, yielding accumulation

11. MOS capacitor structure

12. MOS capacitor- accumulation

13. MOS capacitor- accumulation • Accumulation occurs typically for -ve voltages where the -ve charge on the gate attracts holes from the substrate to the oxide-semiconductor interface. • Depletion occurs for positive voltages. • The +ve charge on the gate pushes the mobile holes into the substrate. • Therefore, the semiconductor is depleted of mobile carriers at the interface and a -ve charge, due to the ionized acceptor ions, is left in the space charge region.

14. MOS capacitor- flat band

15. MOS capacitor- flat band • The voltage separating the accumulation and depletion regime is referred to as the flatband voltage, VFB. • The flatband voltage is obtained when the applied gate voltage equals the workfunction difference between the gate metal and the semiconductor. • If there is a fixed charge in the oxide and/or at the oxide-silicon interface, the expression for the flatband voltage must be modified accordingly.

16. MOS capacitor- depletion

17. MOS capacitor- inversion

18. PART 2: MOSFET

19. MOSFET SYMBOL & CROS SECTION • pmos • nmos • cmos

20. Pmos Operation For pmos

21. Nmos Operation nMOS Operation For nmos

22. Cutoff region: • VGS < VT, any value of VDS • ID = 0 • 2. Linear (or Resistive, or Triode) region: • VGS > VT, VDS <(VGS – VT) • 3. Saturation region: • VGS > VT, VDS > (VGS – VT) “CUTOFF” region: VG < VT Nmos region of operation

23. I-V charateristic for pMOS and nMOS Figure 2 Figure 1

24. I-V Characteristics • Make pMOS is wider than nMOS such that bn = bp

25. Summary NMOS PMOS

26. VIDEO PART 3: Assignment

27. Question 1 • The Transistor data was listed below : • nMOS: K’n= 60µA/V2 , VTO = 0.7V, λ=0.1 V-1, VGS = 5V and VDS = 5V • pMOS: K’p= 60µA/V2 , VTO = 0.7V, λ=0.1 V-1, VGS =- 0. 5V and VDS = -0.5V • Calculate ID current for pMOS. • Calculate the ID current for nMOS. • Based on the ID current , predict the mode operation for pMOS and nMOS (Hint: cutoff,linear,saturation). • Note: VTO = VTH=VT=VTHN= Voltage Threshold

28. PART 4: DC TRANSFER CHARACTERISTIC

29. CMOS INVERTER

30. NOISE MARGIN • Noise margin is related to DC voltage characteristic. • Can determine the allowable noise voltage on the input gate to be • sure that the output will not be corrupted. • Important Parameters: • NML- Low noise margin • NMH- High noise margin • NML = VIL –VOL • NMH = VOH- VIH • VIH= minimun high input voltage • VIL= minimum low input voltage • VOH=minimum high output voltage • VOL= maximum low input voltage

31. Con.... • How much noise can a gate input see before it does not recognise the input

32. PASS-TRANSISTOR • PASS-TRANSISTOR CIRCUITS

33. Cont...

34. SWITCH LEVEL RC DELAY

35. RC DELAY MODEL Cont...

36. RC VALUEs CONT...