A Scalable Parallel H.264 Decoder on the Cell Broadband Engine Architecture. Michael A. Baker, Pravin Dalale, Karam S. Chatha, Sarma B. K. Vrudhula Arizona State University CODES+ISSS (The International Conference on Hardware-Software Codesign and System Synthesis) 2009. Outline.
Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.
Michael A. Baker, Pravin Dalale, Karam S. Chatha, Sarma B. K. Vrudhula
Arizona State University
CODES+ISSS (The International Conference on Hardware-Software Codesign and System Synthesis) 2009
more cores = more performance
SPE: Synergistic Processor Element
SPU: Synergistic Processor Unit
SXU: SPU Core
LS: Local Storage
SMF: Synergistic Memory Flow Control
EIB: Element Interconnect Bus
PPE: PowerPC Processor Element
PPU: PowerPC processor Unit
PXU: Power Processor Unit
MIC: Memory Interface Controller
BIC: Bus Interface Controller
L1: Memory Cache Internal to the CPU
L2: Memory Cache External to the CPU
Possible Intra MB dependencies:
Figure 10: Data structure modifications reducing memory requirements in the local store. W is the width of the video frame in macroblocks.
 Microsoft Corporation. WMV HD Content Showcase. http://www.microsoft.com/windows/windowsmedia/musicandvideo/hdvideo/contentshowcase.aspx
Figure 14: Breakdown of decoder performance by component using a single SPU.
Compare with , our implementation achieves an average 25.23fps or a 23% improvement when decoding similarly encoded video streams on four SPUs.
 H. Baik, K.-H. Sihn, Y. il Kim, S. Bae, N. Han, and H. J. Song. “Analysis and Parallelization of H.264 decoder on Cell Broadband Engine Architecture.” In Signal Processing and Information Technology, pages 791–795. Samsung Electron. Co., Ltd., Suwon, Korea, 2007.