1 / 12

Prototype CERN-option: simulation results

Prototype CERN-option: simulation results. Maria Elena Martin Albarran  UCL et al. Simulations- RFN stabilization. Initial values obtained, show that Voltage control, was stable, using a current bias for the clock very high

mateja
Download Presentation

Prototype CERN-option: simulation results

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Prototype CERN-option: simulation results Maria Elena Martin Albarran UCL et al

  2. Simulations- RFN stabilization Initial values obtained, show that Voltage control, was stable, using a current bias for the clock very high Simulation show that the current has to be lower, and that the whole system behaves as expected with Iclk=50uA-70uA Experimental measurements Simulation 320MHz & Iclk=50uA

  3. Simulations- RFN stabilization Experimental measurements Simulation 320MHz & Iclk=50uA

  4. Simulations- RFN stabilization Initial values obtained, show that Voltage control, was stable, using a current bias for the clock very high Simulation show that the current has to be lower, and that the whole system behaves as expected with Iclk=50uA-70uA RFN (control voltage) can not be monitored usign the oscilloscope, because it affects the measurements (signal not buffered), and simulations will not reproduce the signal

  5. Simulations- Parasitic Extraction • VDD=1.41V, ICLK_BIAS=50uA, RFN~0.65V • DELAY = • NO EXTRACTION DELAY=41.50us • EXTRACTION DELAY=65.00us Delay found with no extraction at all cells Delay found with extraction at all cells

  6. Simulations- Parasitic Extraction • VDD=1.41V, ICLK_BIAS=50uA, RFN~0.65V • DELAY = • NO EXTRACTION DELAY=41.50us • EXTRACTION DELAY=65.00us Delay found with no extraction at all cells Delay found with extraction at all cells

  7. Simulations- Parasitic Extraction • VDD=1.41V, ICLK_BIAS=50uA, RFN~0.65V • DELAY = • NO EXTRACTION DELAY=41.50us • EXTRACTION DELAY=65.00us Delay found with no extraction at all cells Delay found with extraction at all cells

  8. Simulations- Parasitic Extraction • VDD=1.41V, ICLK_BIAS=50uA, RFN~0.65V • DELAY = • NO EXTRACTION DELAY=41.50us • EXTRACTION DELAY=65.00us Simulations- Non CMOS Levels at DLL Test signals not valid range (after diff buff)-> VCDLOUT is non cmos levels VCDLOUT is readout using lvds transmitter pad, no signal there

  9. Simulations- Power Consumption • This shows heating at registers and dll, the non-uniformity is produced by presence of top metal layers -> • Is reasonable?

  10. Simulations- Power Consumption • Simulation Conditions: • Vdd=1.41V, Irclk_bias=50uA, RFN~550mV • Delay/cell(at Tap)=59.6ps • Total Current (through resistor 10mOhm tied to VSS!) • Differential Clock Driver (single to diff Converter) = 112.65uA • Delay Element= 36 x (Diff Buff + Diff Clk + SE Diff Clk)= 36 x (153.87 + 107.06 +75.87) = 36 x 336.80 uA = 12 mA • Resistor String= 47uA

  11. Simulations- Power Consumption • Simulation Conditions: • Vdd=1.41V, Irclk_bias=50uA, RFN~550mV • Register : • write (rms value): • 3.14mA x 1 CHANNEL -> 28.26mA for 9 channels • write & read (rms value): • 3.54mA x 1 CHANNEL -> 31.86mA x for 9 channels results comparable with reality and with previous implementations

  12. Summary • Simulation is following hardware testing • Several other simulations will need to be performed • Power consumption understood • Start-up simulation coherent

More Related