QRC Extraction Hitendra Divecha Sr. Product Marketing Manager SSV Summit November 21st, 2013
Foundry Certified, Signoff Extraction Tool • Leader in supporting technology nodes down to 16/14nm FinFET Extraction QRC Extraction • Fastest Single Corner and Multi-Corner Extraction Performance in 13.1 • Production Proven; Better Accuracy down to FF in 13.1 • Leader in Custom/Analog Designs Extraction • Best and Fastest Convergence in Encounter® and Virtuoso® One Tool Supports Digital and Transistor Flows Using Single Technology File
Tightly Integrated in EDI Providing Best TATand Convergence Silicon Virtual Prototype Power Grid Synthesis Placement Power Routing Same QRC Engine Clock Tree Synthesis Post-CTS Optimization Routing Post-Route Timing/SI Optimization Signoff Extraction Timing, SI, Power Sign-off Single-click execution within EDI for all extraction modes! Signoff Extraction Post-Route Timing/SI Optimization
QRC Extracted ViewUltimate design / debug environment for custom designers Extracted View • Integrated with Virtuoso® • LVS View Supports PVS, Assura, Calibre Faster design closure for custom blocks and top level Integrated with Virtuoso® Design Debug Environment • Back Annotation • Schematic-Layout Cross-probing Simulation Analysis • Integrated with Virtuoso ADE • Easy simulation debug EMIR Analysis • Accurate IR Drop Analysis • Gen models for cell based analysis • Supports VPS-L
Supports all Design Types with Industry-Leading Functionality Substrate Noise Analysis (SNA) • Full 3D substrate model • Full chip and block level • Tightly integrated in Virtuoso Inductance Extraction • Support PEEC method • Sweep from DC100GHz • Supports mutual and Self inductance Custom/Analog and RF Designs MeshR • Used for PowerMos/LCD • Better accuracy for all irregular or wide metal shapes Serdes IP/SRAM/Bitcell Characterization RLCK Reduction • Supports RC and RCLK redux • 20x simulation time reduction, with 5% accuracy • 2.4x total TAT—good accuracy Memory, PowerMos, Image Sensors, etc.
QRC Extraction—Complete FinFET Extraction Solution 16nm FinFET DAC 2013 • Strong collaboration with TSMC to deliver parasitic models to our mutual customers • Key differentiators • Unmatched accuracy • Built upon robust 3D modeling framework • Best cap. and timing accuracy vs TSMC Golden • Unmatched post layout simulationturnaround time (TAT) • Best netlist size and simulation time for a VCO design • 2X smaller netlist • 2.5X faster simulation runtime • Tight integration in Virtuoso for faster design convergence SRAM Characterization Std. Cells Characterization Signoff for Digital & Custom/Analog Designs QRC Bitcell Characterization QRCFS QRC Extraction & QRC Field Solver (QRCFS) 16FF V0.5 Techfiles Available Now!
Key Benefits of EXT13.1 Release • Delivers ~1.5X-2X better performance than competition • - Including ~4X improvement over 12.1.0 1 2 3 • Delivers tighter accuracy against field solver for all advanced node designs • - Slightly conservative with mean, on average, closer to 0 for most advanced node designs • Delivers industry-leading functionality to support FinFET/FDSOI designs • Unmatched accuracy vs Golden at TSMC • 2.5X faster simulation runtime • Faster design convergence in Virtuoso using Cgs flow