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Troisième Partie Chapitre 2 Instructions et adresses Pour ordinateurs séquentiels. Opcode. Oprd. 1. Oprd. 2. Result. Next. Opcode. Oprd. 1. Oprd. 2. Next 1. Next 2. Generic Instructions. Type 1 : Data Handling. Type 2 : Control.

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slide1

Troisième Partie

Chapitre 2

Instructions et adresses

Pour ordinateurs séquentiels

generic instructions

Opcode

Oprd. 1

Oprd. 2

Result

Next

Opcode

Oprd. 1

Oprd. 2

Next 1

Next 2

Generic Instructions

Type 1 : Data Handling

Type 2 : Control

! Inefficient : address of next instruction is stored in

each instruction.

von neumann bottleneck
Von Neumann Bottleneck

For each data handling instruction :

Central

Processing

Unit

opcode

4 addresses

2 operands

Central

Memory

result

architectural goal 1 reduce the bottleneck
Eliminate the “next instruction address”

By using a P register

Reduce size of data handling instructions

By using a stack for expression evaluation

By using registers for intermediate results

Reduce size of control instructions

By using ALU side effects stored in the condition codes register

Augment work done by one instruction

By using vector instructions

Architectural goal 1 :Reduce the bottleneck
program counter
Program Counter

Very often next instruction follows current one

Program

Memory

Control Unit

P register

+ 1

X

I register

program counter 2
Program Counter (2)

Type 1 : Data Handling

Opcode

Oprd. 1

Oprd. 2

Result

Type 2 : Control

Opcode

Oprd. 1

Oprd. 2

Next 1

Default next address is computed in P register

architectural goal 1 reduce the bottleneck1
Eliminate the “next instruction address”

By using a P register

Reduce size of data handling instructions

By using a stack for expression evaluation

By using registers for intermediate results

Reduce size of control instructions

By using ALU side effects stored in the condition codes register

Augment work done by one instruction

By using vector instructions

Architectural goal 1 :Reduce the bottleneck
stack
Stack

Oprd. 1 / Res.

Oprd. 2

Expression evaluation :

Default position of operand(s) and

result(s) is on the stack

. . .

transfer instruction
Transfer Instruction

Data Handling

Opcode

Oprd. 1

Oprd. 2

Result

Data Transfer

Push/Pop

Operand

expression evaluation
Expression Evaluation

a * ( b + c * d ) / ( e + f ) --->a b c d * + * e f + /

d

c * d

b + c * d

a*(b + c * d)

c

b

a

b

a

a

expression evaluation 2
Expression Evaluation (2)

a * ( b + c * d ) / ( e + f ) --->a b c d * + * e f + /

f

e + f

a*(b + c * d) / (e + f)

e

a*(b + c * d)

a*(b + c * d)

0 vs 3 addresses
0 vs. 3 addresses

c = a + b

0 addresses

pusha

pushb

add

popc

3 addresses

adda,b,c

Efficiency depends on type of program

architectural goal 1 reduce the bottleneck2
Eliminate the “next instruction address”

By using a P register

Reduce size of data handling instructions

By using a stack for expression evaluation

By using registers for intermediate results

Reduce size of control instructions

By using ALU side effects stored in the condition codes register

Augment work done by one instruction

By using vector instructions

Architectural goal 1 :Reduce the bottleneck
registers

Load/Store

Reg

Memory Address

Registers

Insert a limited number of addressable registers

in the CPU to store intermediate results

New data transfer instruction format

registers 2
Registers (2)

Data handling instructions become :

3 address

Opcode

Op 1

Op 2

Res

2 address

Opcode

Op 1&

Res

Op 2

Opcode

Op 1&

Res

Op 2

architectural goal 1 reduce the bottleneck3
Eliminate the “next instruction address”

By using a P register

Reduce size of data handling instructions

By using a stack for expression evaluation

By using registers for intermediate results

Reduce size of control instructions

By using ALU side effects stored in the condition codes register

Augment work done by one instruction

By using vector instructions

Architectural goal 1 :Reduce the bottleneck
condition code register
Condition Code Register

Goal : shorten control instructions

Opcode

Oprd. 1

Oprd. 2

Next

Into :

Opcode

Cond

Next

Z

N

V

C

evaluated  instruction

architectural goal 1 reduce the bottleneck4
Eliminate the “next instruction address”

By using a P register

Reduce size of data handling instructions

By using a stack for expression evaluation

By using registers for intermediate results

Reduce size of control instructions

By using ALU side effects stored in the condition codes register

Augment work done by one instruction

By using vector instructions

Architectural goal 1 :Reduce the bottleneck
vector instructions
Vector Instructions

Semantics :

i = 0

Result[i] := Oprd1[i] op Oprd2[i]

i = i + 1

i == Count

no

yes

vector instructions1
Vector Instructions

When the same operation has to be performed

on all elements of a vector

Opcode

Oprd. 1

(1st elt.)

Oprd. 2

(1st elt.)

Result

(1st elt.)

Count

Applications :

Block move in 1 or more dimensions

Arithmetic and Logic operations

architectural goal 2 support for high level languages
Efficient subroutine call

Return address saving allowing reentrance

powerful parameter passing mechanisms

Efficient access to data structures

Rich choice of addressing modes

Efficient handling of block structured languages

Efficient access to local variables

Support for implementation of scope rules

Architectural goal 2 :Support for High Level Languages
architectural goal 2 support for high level languages1
Efficient subroutine call

Return address saving allowing reentrance

powerful parameter passing mechanisms

Efficient access to data structures

Rich choice of addressing modes

Efficient handling of block structured languages

Efficient access to local variables

Support for implementation of scope rules

Architectural goal 2 :Support for High Level Languages
subroutine

xyz :

1

jsr xyz

2

abc :

abc

return

Subroutine

Return address on stack in data memory

subroutine recursion

. . .

. . .

xyz :

1

2,

3

jsr xyz

4

abc :

jsr xyz

rst:

rst

rst

return

abc

. . .

Subroutine : Recursion

. . .

. . .

architectural goal 2 support for high level languages2
Efficient subroutine call

Return address saving allowing reentrance

powerful parameter passing mechanisms

Efficient access to data structures

Rich choice of addressing modes

Efficient handling of block structured languages

Efficient access to local variables

Support for implementation of scope rules

Architectural goal 2 :Support for High Level Languages
addressing modes
Addressing Modes

How is the operand/result named ?

Direct Addressing

xyz

xyz :

Examples :

jump

simple operands

memory

addressing modes 2
Addressing Modes (2)

Indirect Addressing

rst :

xyz

xyz :

rst

Examples :

pointers

call by variable

. . .

memory

addressing modes 3

xyz

Addressing Modes (3)

Indirect Addressing (Register)

R

R:

xyz :

Examples :

pointers

call by variable

stack in central memory

. . .

memory

addressing modes 4
Addressing Modes (4)

Relative addressing

offset

+

base

Examples :

Array

Record

Relative jump

memory

architectural goal 2 support for high level languages3
Efficient subroutine call

Return address saving allowing reentrance

powerful parameter passing mechanisms

Efficient access to data structures

Rich choice of addressing modes

Efficient handling of block structured languages

Efficient access to local variables

Support for implementation of scope rules

Architectural goal 2 :Support for High Level Languages
block structured languages
Block Structured Languages

A program is a set of nested blocks

{ ... } // RED

{ ... } // GREEN

{ ... } // PURPLE

{ ... } // BLUE

block structured languages1

int a

float b

char c

{ ... a =...; b =...; c =...; ... }

X

{ ... a =...; b =...; c =...; ... }

X

{ ... a =...; b =...; c =...; ... }

X

X

{ ... a =...; b =...; c =...; ... }

Block Structured Languages

An identifier can be used everywhere within the block where it is declared

block structured languages2

int a

float b

char a

{ ... a = ‘$’; b =...; ... }

X

{ ... a = 2; b =...; c =...; ... }

X

{ ... a =...; b =...; c =...; ... }

X

X

{ ... a = 5; b =...; c =...; ... }

Block Structured Languages

A global identifier can be redefined The local definition dominates

block structured languages3
Block Structured Languages

The case of C, C++, Java

Global block

main red

{ ... { } }

green

{ ... { } { } }

purple

{ ... { } { } }

No nested functions !

block structured languages4
Block Structured Languages

Classical block structured languages

Program MyProgram

Function Red

{ ... }

Function Green

{ ... }

Function Purple

{ ... }

{ ... }

The outer block corresponds to the main program

Each function (procedure) is one block

data addresses in block structured languages
Variables are declared in a Block

Their address has two parts:

The identifier of the block

The position in that block (offset)

Block identifiers can be expressed by specifying relative nesting levels

Block id.

Rel.nesting level

Offset

Offset

Data Addresses in Block Structured Languages
data addresses in c c java
Variables are declared in a Block

Nesting within a function can be handled statically by the compiler

During execution, all local variables of a function are grouped in one block, the “activation record” of the function

Addresses defined per function

Function id.

Offset

Data Addresses in C, C++, Java
data memory usage 1 for c like languages
Data Memory Usage(1)(for C-like languages)

Global block

main

Data Memory :

… yellow; …red;…

yellow;

… green; …

RED;

red

… green;…

GREEN;

green

Activation Records

Operating System

data memory usage 2
Data Memory Usage(2)

Global block

main

Data Memory :

… yellow; …red;…

yellow;

… green; …

RED;

red

… green;…

main

GREEN;

green

Activation Records

Return Address

Operating System

data memory usage 3
Data Memory Usage(3)

Global block

main

Data Memory :

… yellow; …red;…

yellow;

… green; …

RED;

red

yellow

… green;…

main

GREEN;

green

Operating System

data memory usage 4
Data Memory Usage(4)

Global block

main

Data Memory :

… yellow; …red;…

yellow;

… green; …

green

RED;

red

yellow

… green;…

main

GREEN;

green

Operating System

data memory usage 5
Data Memory Usage(5)

Global block

main

Data Memory :

… yellow; …red;…

yellow;

… green; …

RED;

red

yellow

… green;…

main

GREEN;

green

Operating System

data memory usage 6
Data Memory Usage(6)

Global block

main

Data Memory :

… yellow; …red;…

yellow;

… green; …

RED;

red

… green;…

main

GREEN;

green

Operating System

data memory usage 7
Data Memory Usage(7)

Global block

main

Data Memory :

… yellow; …red;…

yellow;

… green; …

RED;

red

red

… red;…

main

GREEN;

green

Operating System

data memory usage 8
Data Memory Usage(8)

Global block

main

Data Memory :

… yellow; …red;…

yellow;

… green; …

red

RED;

red

red

… red;…

main

GREEN;

green

Operating System

data memory usage 9
Data Memory Usage(9)

Global block

main

Data Memory :

… yellow; …red;…

yellow;

red

… green; …

red

RED;

red

red

… red;…

main

GREEN;

green

Operating System

data memory usage 10
Data Memory Usage(10)

Global block

main

Data Memory :

… yellow; …red;…

yellow;

… green; …

red

RED;

red

red

… red;…

main

GREEN;

green

Operating System

data memory usage 11
Data Memory Usage(11)

Global block

main

Data Memory :

… yellow; …red;…

yellow;

… green; …

RED;

red

red

… red;…

main

GREEN;

green

Operating System

data memory usage 12
Data Memory Usage(12)

Global block

main

Data Memory :

… yellow; …red;…

yellow;

… green; …

RED;

red

… green;…

main

GREEN;

green

Operating System

data memory usage 13
Data Memory Usage(13)

Global block

main

Data Memory :

… yellow; …red;…

yellow;

… green; …

RED;

red

… green;…

GREEN;

green

Operating System

base register
Base Register

Data Memory

Base Register

ORANGE

Activation Record

YELLOW

Activation Record

BLUE

Activation Record

dynamic links
Dynamic Links

Data Memory

Base Register

ORANGE

Activation Record

YELLOW

Activation Record

BLUE

Activation Record

static links
Static Links

Data Memory

Base Register

ORANGE

Activation Record

YELLOW

Activation Record

GREEN

Activation Record

Dynamic

links

Static

links

PURPLE

Activation Record

BLUE

Activation Record

architectural goal 2 support for high level languages4
Efficient subroutine call

Return address saving allowing reentrance

powerful parameter passing mechanisms

Efficient access to data structures

Rich choice of addressing modes

Efficient handling of block structured languages

Efficient access to local variables

Support for implementation of scope rules

Architectural goal 2 :Support for High Level Languages
function parameters

CCC abc

CCC uvw

Function Parameters

Actual Parameters

Formal Parameters

DoCCC(abc)

Subroutine DoCCC(xyz)

CCC xyz

End DoCCC

DoCCC(uvw)

function parameters1
Formal parameter are declared in the procedure.

Actual parameters appear in the procedure call.

Formal and actual parameters MUST have STRICTLY the same type

Association between actual and formal parameters is positional:

PROCEDURE DoIt(a,b,c) DoIt(x,y,z)

a ~ x ; b ~ y; c ~ z;

Function Parameters
parameter passing
Parameter Passing

Data Memory

Base Register

Called Block

Activation Record

Parameters

Static

link

Dynamic

link

Calling Block

Activation Record

parameter passing by value
Parameter Passing by value

Data Memory

Base Register

Called Block

Activation Record

Value of

Actual Parameters

Static

link

Dynamic

link

Calling Block

Activation Record

The actual parameter can be an expression

parameter passing by reference
Parameter Passing by Reference

Data Memory

Base Register

Called Block

Activation Record

Actual parameters are

accessed through

Indirect addressing

Static

link

Address of

Actual Parameters

Dynamic

link

Calling Block

Activation Record

The actual parameter must be a variable

value returned by function
Value Returned by Function

Data Memory

Base Register

Called Block

Activation Record

Actual Parameters

Static

link

Dynamic

link

Returned Value

Calling Block

Activation Record