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Nanoscale Silicon Technology. Presenters Topics. Mike Duffy Double-gate CMOS. Eric Dattoli Strained Silicon. Alain Espinosa Thin Gate Insulators. Challenges as CMOS feature sizes decrease. Carrier Mobility reduction Threshold voltage (V T ) control reduction

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Nanoscale Silicon Technology

Presenters Topics

Mike Duffy Double-gate CMOS

Eric Dattoli Strained Silicon

Alain Espinosa Thin Gate Insulators


Challenges as cmos feature sizes decrease l.jpg

Challenges as CMOS feature sizes decrease

  • Carrier Mobility reduction

  • Threshold voltage (VT) control reduction

  • 3. Off-state leakage increase

  • 4. Power consumption increase


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Band diagram when on:

A basic MOSFET:

Eeff


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Problem 1: Carrier Mobility Decreases as Channel length decrease and Vertical Electric fields increase

Mobility versus technology scaling trend for Intel process

technologies. From (Thompson 2004)


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Problem 2: V decrease and Vertical Electric fields increaseT Rolloff as Channel length decreases

Substrate-Strained Silicon Technology: Process Integration

H. C.-H. Wang, IEDM 2003

One common solution : Increasing Channel Doping reduces Short Channel Effect


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(Problem 2) V decrease and Vertical Electric fields increaseT Rolloff explained by Short Channel Effect

This problem is addressed by Double Gate Technology


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Problem 3: Tunneling Through Gate Oxide (off state current)

Eox

This problem is addressed by Strained Silicon, and Thin-Insulator technology


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Problem 4: Wattage/Area increases as density increases current)

MOSFET Scaling Trends, Challenges, and Potential Solutions Peter M. Zeitzoff and James E. Chung. IEEE CIRCUITS & DEVICES MAGAZINE ¦ JANUARY/FEBRUARY 2005

This problem is addressed by Double Gates, Straining, and thin Gate Insulators


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Double Gate MOSFET current)

  • Features:

    • Upper and lower gates control the channel region

    • Ultra-thin body acts as a rectangular quantum well at device limits

    • Directly scalable down to 20 nm channel length


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Band Structure current)


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Layout current)

  • Type I : Planar Double Gate

  • Type II: Vertical Double Gate

  • Type III: Horizontal Double Gate (FinFET)



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Reduced Channel and Gate Leakage current)

  • Short channel effects are seen in Standard silicon MOS devices

  • DGFET offers greater control of the channel because of the double gate

  • Gate leakage current is prevented by a thick gate oxide


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Threshold Voltage Control current)

  • Silicon MOS Transistor:

    • Increased body doping used to control VT for short channel

    • Small number of dopant atoms for very short channel

    • Lowest VT achievable is .5V

  • Double Gate FET :

    • Increased body doping

    • Asymmetric gate work functions (n+ / p+ gates)

    • Metal gate

    • VT of .1V achievable through work function engineering


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Increased Carrier Mobility current)

  • Silicon MOS Transistor:

    • Carrier scattering from increased body doping

    • Transverse electric fields from the source and drain reduce mobility

  • Double Gate FET:

    • Lightly doped channel in a DGFET results in a negligible depletion charge

    • Asymmetric gate: experiences some transverse electric fields

    • Metal gate: transverse electric field negligible with increased channel control


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Reduced Power Consumption current)

  • Double Gate coupling allows for higher drive currents at lower supply voltage and threshold voltage

  • Energy is a quadratic function of supply voltage

  • Reduced channel and gate leakage currents in off state translate to huge power savings

  • Separate control of each gate allows dynamic control of VT :

    • Simplified logic gates would save power and chip area



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Challenges Facing Double Gate Technology current)

  • Identically sized gates

  • Self-alignment of source and drain to both gates

  • Alignment of both gates to each other

  • Connecting two gates with a low-resistance path


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Ultimate Double Gate Limits current)

  • Thermionic emission above the channel potential barrier:

    • Short channel effects lower potential barrier

  • Band-to-band tunneling between body and drain pn junction:

    • Body-drain electric field increases tunneling probability

  • Quantum mechanical tunneling directly between source and drain:

  • Extremely small channel lengths correspond to narrow potential barrier width

  • 4) Other effects of quantum confinement in the thin body


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Lattice Constants: current)

Si 5.431 Angstrom

Ge 5.658 Angstrom

Si/Ge Alloys

Alloys are uniform crystal structures containing two different materials which posess the same ordering property.

Can create Si1-xGex alloys where x is a number from 0.0 to 1.0

This is possible since both materials create diamond type lattices and their lattice constants are close.

Lattice constant of alloy is determined by Vegard’s Law, which is a linear average between the constants of Si and Ge.

aalloy = (1-x) • aSi + x • aGe

Note: other material parameters change: e.g. bandgap



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Si and Si current)1-xGex Alloy Heterostructures

A Heterostructure is a semiconductor structure in which the material

composition changes with position. Heterostructure devices are made

by using Molecular Beam Epitaxy to grow a different material on a substrate.

Performance Projections of Scaled CMOS Devices and Circuits With Strained Si-on-SiGe Channels. Jerry G. Fossum, Fellow, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 4, APRIL 2003


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Si current)

Ge

Si

Ge

Physics of Semiconductors and their Heterostructures. Jasprit Singh



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Required to lay heterolayer within a constrained thickness current)

Substrate-Strained Silicon Technology: Process Integration

H. C.-H. Wang, IEDM 2003


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Scale Picture of Strained Si NMOS Heterostructure current)

Improved Hot-Electron Reliability in Strained-Si nMOS

David Onsongo, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 12, DECEMBER 2004 2193


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Strain Engineering current)

X

Y

Z

Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering

C.-H. Ge, IEDM 2003

<100> Strained-SiGe-Channel p-MOSFET with Enhanced Hole Mobility and Lower Parasitic Resistance

v Masashi Shima FUJITSU Sci. Tech. 2003

<100> Orientated Wafer


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Biaxial tension in Strained Si on SiGe MOSFET current)

Fabrication and Analysis of Deep Submicron Strained-Si N-MOSFET’s

Kern (Ken) Rim, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 7, JULY 2000


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.19 m current)0 < .98 m0

LH

HH

Scaling Planar Circuits

IEEE Circuits & Device Magazines Jan/Feb 2004


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Z current)

Rim (2000)

X

Carriers in channel travel along X-Y plane in k-space

Y

Carriers move along [010] or [100] direction

Applies to common (001) oriented

Silicon substrate

Same Z or [001] Axis in Real Space


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Relationship between effective mass and carrier mobility current)

Carrier mobility is given by:μn= q • t mn*Current Density depends on Carrier mobility:Jx = q • n • μn •εxThis decrease in carrier mobility is addressed by Strained Silicon. Specifically, we’ll see that mn*is reduced


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Bonus: Tunneling through Gate Oxide decreases with Strained Silicon

Channel Structure Design, Fabrication and Carrier Transport Properties

of Strained-SYSiGe-On-Insulator (Strained-SOI) MOSFETs

S. Takagi+

IEDM 2003


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Problem To Solve: Silicon

We will use the WKB Approximation to calculate how much the Gate Tunneling Current is reduced by increasing the insulator/channel barrier height.

Remember, Straining increases the insulator/channel barrier height.

Transmission Probability depends on meff, Electric Field across barrier(Eox) ,and barrier height (Φox)


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How To Find Si/SiO2 Barrier Height and Eox of Triangular Barrier

Eox

Unstrained:

Φox=3.2 eV

Strained:

Φox=3.3 eV

Device Design for Sub-0.1µm MOSFETs for Sample and Hold Circuits. 2003 Mayank Kumar Gupta


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Compare 5x difference in Gate Current to difference in Jg (gate current density) at Eox = 8 MV/cm

1/(8 MV/cm) = 0.125

ln (J unstrained) = -12.9

ln (J strained) = -14.6

Their difference is exp(1.7) = 5.5

Which is very close to the theoretical result of 4.7x from the WKB Approximation. This difference isn’t constant, at:

• Eox = 7.4 MV/cm, there is about a 7.5x difference

• Eox = 9.1 MV/cm, there is about a 4.5x difference


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Difference in Junstrained/Jstrained as Eox varies is predicted by the theoretical WKB approximation

Compares to experimental difference of 4.5x


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Compares to experimental difference of 7.5x predicted by the theoretical WKB approximation


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Effects of Eox on Tunneling Current through Gate predicted by the theoretical WKB approximation

Improved Hot-Electron Reliability in Strained-Si nMOS

David Onsongo, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 12, DECEMBER 2004 2193


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Better Way to Engineer Strain predicted by the theoretical WKB approximation

A 90-nm Logic Technology Featuring Strained-Silicon Scott E. Thompson, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 11, NOVEMBER 2004


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Strain Applied to NMOSFETs predicted by the theoretical WKB approximation

MOSFET Current Drive Optimization Using Silicon Nitride Capping Layer for 65-nm Technology Node. S. Pidin 2004 Symposium on VLSI Tech Digest


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Advantage over Si on SiGe method predicted by the theoretical WKB approximation


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This method improves Drain Currents for: predicted by the theoretical WKB approximation

PMOS

NMOS

A 90nm High Volume Manufacturing Logic Technology Featuring

Novel 45nm Gate Length Strained Silicon CMOS Transistors. IEDM 2003


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SiO predicted by the theoretical WKB approximation2 limitations

  • Scaling

  • Power Consumption

  • One solution is using High-k dielectric

  • material


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High-k dielectric material predicted by the theoretical WKB approximation

  • Are used to minimize tunneling current

  • and the out diffusion of boron from the

  • gate.

  • Types

  • 1) 4 < k < 10 ; SiNx

  • 2) 10 < k < 100; Ta2O5, Al2O3, TiO2

  • 3) 100 < k

  • What we are looking for in High-k dielectrics?


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One Example of High-k dielectrics predicted by the theoretical WKB approximation

  • Al2O3

  • I-V Plot for different thicknesses on Si(100)


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Al predicted by the theoretical WKB approximation2O3 continued

  • Dielectric Constant (k)

  • Recent study show Al2O3 tunneling dielectrics <1nm thick are superior to previously used Si3N4 and SiO2


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Some recent of High-k dielectrics predicted by the theoretical WKB approximation

  • Al2O3 film have been used to make 1Gbit DRAM

  • Al2O3 and HfO2 have been used to produce a Vertical Replacement-gate (VRG) n-Mos.


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-Conclusions on High-k dielectrics predicted by the theoretical WKB approximation


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Thank you predicted by the theoretical WKB approximation

Questions?


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Side Problem: Increasing Channel Doping decreases mobility predicted by the theoretical WKB approximation

Solid State Electronic Devices. Streetman


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