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Lava PowerPoint Presentation

Lava

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Lava

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  1. Lava Mary Sheeran, Koen Claessen Chalmers University of Technology Satnam Singh, Xilinx

  2. Lava Not so much a hardware description language More a style of circuit description Emphasises connection patterns Think of Lego

  3. f g Behaviour and Structure f g f ->- g

  4. g f Parallel Connection Patterns f -|- g

  5. f f f f map f

  6. Four Sided Tiles

  7. Column

  8. fa Full Adder in Xilinx Lava cout b sum a cin fa (cin, (a,b)) = (sum, cout) where part_sum = xor (a, b) sum = xorcy (part_sum, cin) cout = muxcy (part_sum, (a, cin))

  9. fa fa fa Generic Adder adder = col fa

  10. Top Level adder16Circuit = do a <- inputVec ”a” (bit_vector 15 downto 0) b <- inputVec ”b” (bit_vector 15 downto 0) (s, carry) <- adder1 (a, b) sum <- outputVec ”sum” (s++[carry]) (bit_vector 16 downto 0) ? circuit2VHDL ”add16” adder16Circuit ? circuit2EDIF ”add16” adder16Circuit ? circuit2Verilog ”add16” adder16Circuit

  11. 114 Lines of VHDL library ieee ; use ieee.std_logic_1164.all ; entity add16 is port(a : in std_logic_vector (15 downto 0) ; b : in std_logic_vector (15 downto 0) ; c : out std_logic_vector (16 downto 0) ) ; end entity add16 ; library ieee, unisim ; use ieee.std_logic_1164.all ; use unisim.vcomponents.all ; architecture lava of add16 is signal lava : std_logic_vector (0 to 80) ; begin ... lut2_48 : lut2 generic map (init => "0110") port map (i0 => lava(5), i1 => lava(21), o => lava(48)) ; xorcy_49 : xorcy port map (li => lava(48), ci => lava(47), o => lava(49)) ; muxcy_50 : muxcy port map (di => lava(5), ci => lava(47), s => lava(48), o => lava(50)) ; lut2_51 : lut2 generic map (init => "0110") port map (i0 => lava(6), i1 => lava(22), o => lava(51)) ; xorcy_52 : xorcy port map (li => lava(51), ci => lava(50), o => lava(52)) ; muxcy_53 : muxcy port map (di => lava(6), ci => lava(50), s => lava(51), o => lava(53)) ; lut2_54 : lut2 generic map (init => "0110") port map (i0 => lava(7), i1 => lava(23), o => lava(54)) ; ...

  12. EDIF... (edif add16 (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timeStamp 2000 11 19 15 39 43) (program "Lava" (Version "2000.14")) (dataOrigin "Xilinx-Lava") (author "Xilinx Inc.") ) ) ... (instance lut2_78 (viewRef prim (cellRef lut2 (libraryRef lava_virtex_lib)) ) (property INIT (string "6")) (property RLOC (string "R-7C0.S1")) ) … (net lava_bit38 (joined (portRef o (instanceRef muxcy_38)) (portRef ci (instanceRef muxcy_41)) (portRef ci (instanceRef xorcy_40)) ) )

  13. Xilinx FPGA Implementation • 16-bit implementation on a XCV300 FPGA • Vertical layout required to exploit fast carry chain • No need to specify coordinates in HDL code

  14. 16-bit Adder Layout

  15. Four adder trees

  16. No Layout Information

  17. cout fa b sum a cin Full Adder in Chalmers Lava fa (cin, (a,b)) = (sum, cout) where part_sum = xor2 (a, b) sum = xor2 (part_sum, cin) cout = mux (part_sum, (a, cin))

  18. import Lava fa (cin,(a,b)) = (sum,cout) where part_sum = xor2(a,b) sum = xor2(part_sum,cin) cout = mux(part_sum,(a,cin)) Main> simulate fa (high,(high,high)) (high,high)

  19. import Lava import Patterns fa (cin,(a,b)) = (sum,cout) where part_sum = xor2(a,b) sum = xor2(part_sum,cin) cout = mux(part_sum,(a,cin)) add = row fa Main> simulate add (low,[(low,high),(high,low),(low,high)]) ([high,high,high],low)

  20. import Lava import Arithmetic fa (cin,(a,b)) = (sum,cout) where … checkFullAdd ins = ok where out1 = fa ins out2 = fullAdd ins -- Lava built-in fullAdder ok = out1 <==> out2 Main> vis checkFullAdd Vis: ... (t=0.7) Valid.

  21. In file Verify/circuit.mv .model circuit.inputs i0.inputs i1.inputs i2.outputs good.table -> low0.latch low initt.reset initt1.table -> w21.table i0 -> w90 01 1.table i1 -> w100 01 1.table w9 w10 -> w80 0 00 1 11 0 11 1 0 ….. .table initt w2 w1_x -> w1 1 - - =w2 0 - - =w1_x .table w1 -> good 0 0 1 1 .end

  22. import Lava import Arithmetic fa (cin,(a,b)) = (sum,cout) where … checkFullAdd ins = ok where out1 = fa ins out2 = fullAdd ins -- Lava built-in fullAdder ok = out1 <==> out2 Main> satzoo checkFullAdd Vis: ... (t=0.1) Valid.

  23. In file Verify/circuit.cnf In file Verify/circuit.cnf.out c Generated by Lava2000 c c i0 : 6 c i1 : 7 c i2 : 8 p cnf 21 57 -5 6 7 0 -5 -6 -7 0 5 -6 7 0 5 -7 6 0 -4 5 8 0 -4 -5 -8 0 4 -5 8 0 4 -8 5 0 Parsing DIMACS Solving (randomize) 10000/38 (0.00 %). Computing static variable order. restarts : 0 conflicts : 10 learnt_clauses : 5 forgotten_clauses : 3 decisions : 10 propagations : 79 inspect_binary : 49 inspect_normal : 194 inspect_learnt : 2 CPU time : 0 s UNSATISFIABLE real 0.1 user 0.0 sys 0.0 ….. 11 -12 -21 0 -11 12 0 -11 21 0 1 -2 -11 0 -1 2 0 -1 11 0 -1 0

  24. Equal? F G Equivalence Checking

  25. Equal? F G View as property checking

  26. Prop F ok Synchronous Observer • Only one language (so easier to use) • Safety properties • Used in verification of control programs

  27. Different styles deland (a,b) = c where newa = delay low a newb = delay low b c = and2(newa,newb) deland1 = (delay low -|- delay low) ->- and2 deland2 = delay (low,low) ->- and2 deland3 = delay zero ->- and2

  28. Simulating sequential circuits Main> simulateSeq deland [(low,low),(high,low),(high,high),(low,low)] [low,low,low,high] Main> simulateSeq deland2 [(low,low),(high,low),(high,high),(low,low)] [low,low,low,high]

  29. Checking equivalence anddel = and2 ->- delay low prop_Equivalent circ1 circ2 a = ok where out1 = circ1 a out2 = circ2 a ok = out1 <==> out2 Main> vis (prop_Equivalent deland anddel) Vis: ... (t=0.2) Valid. Main> smv (prop_Equivalent deland3 anddel) Smv: ... (t=0.4) Valid.

  30. In Verify/circuit.smv DEFINE w5 := 0; DEFINE w6 := i0; ASSIGN init(w4) := w5; ASSIGN next(w4) := w6; DEFINE w8 := i1; ASSIGN init(w7) := w5; ASSIGN next(w7) := w8; DEFINE w3 := w4 & w7; DEFINE w10 := w6 & w8; ASSIGN init(w9) := w5; ASSIGN next(w9) := w10; DEFINE w2 := !(w3 <-> w9); DEFINE w1 := !(w2); SPEC AG w1 -- Generated by Lava2000 MODULE main VAR w1 : boolean; VAR w2 : boolean; VAR w3 : boolean; VAR w4 : boolean; VAR w5 : boolean; VAR w6 : boolean; VAR i0 : boolean; VAR w7 : boolean; VAR w8 : boolean; VAR i1 : boolean; VAR w9 : boolean; VAR w10 : boolean;

  31. Many delays delayN 0 init = id delayN n init = delay init ->- delayN (n-1) init dAnd n = delayN n (low,low) ->- and2 andD n = and2 ->- delayN n low Main> smv (prop_Equivalent (dAnd 10) (andD 10)) Smv: ... (t=0.9) Valid. Main> smv (prop_Equivalent (dAnd 15) (andD 15)) Smv: ... (t=2:30.3) Valid. Same verification for 20 takes more than 35 minutes

  32. Note Could be viewed as Lustre (or similar) embedded in Haskell Generic circuits and connection patterns easy to describe (the power of Haskell) Verify FIXED SIZE circuits (squeezing the problem down into an easy enough one)

  33. Working on lists G F parl F G = halveList ->- (F -|- G) ->- append

  34. two f f f

  35. f f f f two (two f)

  36. Many twos twoN 0 circ = circ twoN n circ = two (twoN (n-1) circ)

  37. Interleave f f ilv f unriffle ->- two f ->- riffle

  38. Many interleaves ilv (ilv (ilv C))

  39. Many interleaves ilvN 0 circ = circ ilvN n circ = ilv (ilvN (n-1) circ)

  40. Wiring id2 swap

  41. Butterfly bfly circ bfly circ

  42. Defining Butterfly bfly 0 circ = id bfly n circ = ilvN (n-1) circ ->- two (bfly (n-1) circ)

  43. Butterfly Layout on an FPGA

  44. Bitonic merger compInt [x,y] = [imin(x,y), imax(x,y)] compBit [x,y] = [and2(x,y), or2(x,y)] Main> simulate (bfly 3 compInt) [1,3,5,7,8,6,4,2] [1,2,3,4,5,6,7,8] Main> simulate (bfly 2 compBit) [low,high,low,high] [low,high,low,high]

  45. Describe connection pattern Then plug in variety of components, including bit-serial etc. (see work of Vuillemin) Sorters and mergers verified using 0-1 principle and SAT-solver (see Knuth vol. 3) Used higher order functions and polymorphism

  46. Reduction tree for multiplier 5 4 4 3 3 carries 2 Fast Adder

  47. multiply (as,bs) = p1:ss where ([p1]:[p2,p3]:ps) = prods_by_weight (as,bs) is = redArray ps ss = binaryAdder ([p2,p3]:is) redArray = addEmpty ->- row compress ->- first

  48. f-cell compress

  49. h1-cell other cases h-cell insC

  50. 5 6 4 3 2 carries 5 4 3