Design of Realtime, 50 to 100 Ms/s, Signal Parameter Estimation Using FPGAs. R. Bassett, J. Zaino, T. S. Sun, D. Bateman Sanders, A Lockheed Martin Company Nashua, NH 030610868. Presented by: Bob Bassett (603) 8858272 robert.l.bassett@lmco.com.
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Design of Realtime, 50 to 100 Ms/s, Signal Parameter Estimation
Using FPGAs
R. Bassett, J. Zaino, T. S. Sun, D. Bateman
Sanders, A Lockheed Martin Company
Nashua, NH 030610868
Presented by:
Bob Bassett
(603) 8858272
robert.l.bassett@lmco.com
This material is based upon work supported by USAF AFMC AFRL under contract number F3060298C0104. Any opinions, findings and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the USAF AFMC AFRL.
9/26/00
Use of FPGAs to implement Matlab modeled
math functions in synchronous pipelines
A/D Estimation
Reference design, a digital starring receiverDelay
NB Filter
Demodulator
Filter
Bank
Digital
LO
Energy Detection
Tune
What does the signal
look like?
 Rectangular to polar conv
 Noise floor estimation
 Programmable detection rules
 Coarse frequency estimate
 Magnitude estimate
 Time of arrival estimate
Is a signal present?
Where is it?
Goals:
1. Exploit advantages in A/D technology
2. Explore size / performance trades and opportunities for approximation
3. Architectures for high sample rate processing (pipelining and parallelism)
5. Explore capabilities of high level design tools
6. Implement on COTS modules
3 x Virtex
1000
WildStar PCI
Currently running on single FPGA
notebook based WildCard
Plans to migrate to triple FPGA
workstation based PCI Wildstar
WildCard
Virtex
300
Carryon, Point of Collection AnalysisDesktop/Server
Xilinx
Xcv300
SRAM
Memory
SRAM
Memory
CardBus
Interface
Annapolis Microsystems Inc.
WildCard PCMCIA Module
PC
Filter Bank
(4 to 16 Channels)
Rectangular
to Polar
Noise Floor
Estimates
Threshold
Frequency Est
Tune Command
Arbitrator
50 Ms/S
at
I (12 bits),
Q (12 bits)
.
.
.
.
.
.
.
.
.
.
.
.
Amplitude &
Time of Arrival
Estimates
Samples
Noise
Floor
Estimator
Detection
Decision
Coarse
Frequency
Estimator
Tune Commands
Magnitude
Amplitude
Rectangular
to
Polar
Convert
Create
Desc
Amplitude
Measure
I
Q
Signal
Detection
PW
Pulse Width
Measure
Signal
Descriptors
TOA
Time of Arrival
Measure
Frequency
Frequency
Measure
Phase
Bus
Arbitration
Timing and
Control
Synchronous pipelines run at incoming sample rates
Control
Q Estimation
Rectangular to
Magnitude
Polar Conversion
I
Phase
Rectangular to Polar Conversion IssuesWhy:
In phase/Quadrature (I,Q or rectangular form) is convenient for sampling and filtering
Accuracy approximation, usage dependent
0 0 0 0 1 1 0 0 0 1 1 1 Data Estimation
0 0 1 0 1 1 0 0 0 1 1 1 Data
1110 9 8 7 6 5 4 3 2 1 0 bit pos
1110 9 8 7 6 5 4 3 2 1 0 bit pos
Rectangular to Polar Conversion OperationLog Magnitude=Log( \/I2+Q2)
Phase = arctan (I/Q)
Lookup Table
Log Magnitude
and
Phase
Reg
Logic
I (12)
Q(12)
12
to
8 bits
I (8)
Q (8)
Scale
LMag (8)
Phase (8)
LMag (8)
Phase (8)
I (12 bits)
Q (12 bits)
Scale
Factor
Scale
Factor
8 LSBs used for table lookup
(when there are no higher bits)
4 MSBs determine
scale factor
Force to 0
Time and frequency cells
are averaged to generate
noise floor estimate
Cell under test
for detection.
Guard cells
Guard cells
Time cells (8 + 8)
72 dB
Frequency
Cells (16)
54 dB
Noise floor
set point
3 bits= 18dB
0 mag
Reg Estimation
÷ 8
Reg
Reg
Integrate Incoming Samples Over Time, within FPGA, to Estimate Noise FloorReplicated twice per channel (2x16)
Once before and once after
cell under test
Sample Pipeline
Incoming
Sample
Magnitudes
Reg
sn8
sn
Acc = 0
1
8
Average =
((Acc + sn)  sn8)

+
Acc
Noise Estimate
Accumulator
Noise
Floor
Estimate
(sufficient for frequency estimate), and
(minimizes pulse fracturing).
3 x 5 Moving Map
<
Frequency Slots
(Filter Channels)
x
x
o
o
<
Time Slots (Samples)
Cell Under
Test for
Detection
Threshold based time of arrival estimates are dependent on magnitude estimate
Leading edge slope
Average magnitude to
estimate amplitude
Amplitude estimation
Time of crossing 50% threshold
determines TOA
Profile of pulse magnitude
Radar
Leading Edge
varies as
magnitude varies
Original
Multipath
Stretched
Sum of original
and multipath
It is generally more important that the measurements be consistent than that they be exact.
Use a technique that provide the most consistent answer.
Sample Data
Memory
Edge Detection
Index to start of Pulse,
Peak Amp, Noise Est
Sample by Sample Operations
Detection Queue
Noise Estimator
ComputationEngine
Dual Port
Memory
Calculate Amplitudes
for Reference Points
Scan Edge for
Qualifying Points
Results
Memory
Calculate TOA
Calculate
Slope & Intercept
Accumulate
“Best Fit” Factors
N
Σ
1
N
Amplitude =
sn
1
Time series magnitude Plot,
output of Rectangular to polar converter
Amplitude:
Average magnitude over
a first N samples of the pulse
after point of detection
Amplitude Estimation Techniques
 Average over the duration of the pulse,
accurate but susceptible to pulse on pulse corruption
 Peak from matched filter,
accurate but requires knowledge of original pulse
 Average over the first portion or center half of pulse
 Estimate rise time, calculate pulse width or use a fixed delay to
start of the integration window
Goals:
High throughput
2x to 4x improved accuracy
Challenges:
Dependencies
 Noise floor est, Amplitude est
Performance
 Sample by sample processing (in progress)
I
Q
SAMPLE
CLOCKS
Q
Rectangular to
Magnitude
Polar Conversion
I
Phase
1
Polar form
frequency is
rate of rotation of
magnitude vector.
2 = arctan(I/Q)
Estimate frequency
by approximating.
Frequency =
d /dt as (2  1)/t.
t
6
4
2
0
Caution, phase angle is ambiguous
6
4
phase
angle
2
0
Phase angle may range from 0 to n and beyond,
but only the angles 0 to 2 can be represented
(trigonometry).
When calculating =n+1  n,
if n+1 < n then = +2
time samples
Original LFM pulse  yellow
Measured LFM
signal  blue
The output:
Measured frequency and the
error in measured frequency
The input::
Magnitude and phase
Can you see the
signal??
Frequency error as a percentage of channel width
A linear FM
pulse
Results using synthesized VHDL,
next step, the FPGA
The FPGA algorithm can see it.
Incoming Signals Being Detected
Sample
Phases
4
Σ
1
4ts
Frequency =
1
Pipeline of delayed
Phase differences

Reg
Reg
Reg
Reg
Reg
+
+
+
÷ 4
Reg
Frequency
estimate
Coarse Frequency Estimator logicsign
Calculate phase difference
between samples
+
2
Integrate phase differences
over 5 samples and
divide by 4
Channelized Receiver Analysis and Visualization Tool (CRVT)Rapid Prototyping for Digital Receivers, Rapidly Iterate Alternative Designs and Test Cases
Tools automate the routine process tasks, provide visualization of results and speed iteration.
Test Bench Engineering
Function
Being Developed
Performance
Visualization
RAPID Prototyping of RF Receivers with FPGAs; From Signals, Responses and Algorithms to Gates on Silicon
Algorithm Analysis
Requirements
• SNR analysis
• Alternative implementations
• Functional approximations
Floating Point
Simulation
Algorithm
Rearrangement
Bit Accurate
Simulation
Alternative Implementations
Algorithm
Rearrangement
VHDL
Modeling
Alternative Implementations
• Timing and sizing estimation
• Scheduling – FSM and contexts
• Partitioning
Synthesis
FPGA Realization
Develop for Real Time test capability