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Bubonic Assembly Language

Bubonic Assembly Language. CS232 Computer Architecture I – Team R. Douglas Jeffries Himanshu Narayana David Rickard. February 13, 2002. Overview. Special Features Instruction Set Development Datapath Control Testing Demonstration. Special Features. Memory copy instruction

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Bubonic Assembly Language

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  1. Bubonic Assembly Language CS232 Computer Architecture I – Team R Douglas Jeffries Himanshu Narayana David Rickard February 13, 2002

  2. Overview • Special Features • Instruction Set • Development • Datapath • Control • Testing • Demonstration

  3. Special Features • Memory copy instruction • Direct copy between memory locations • Return address register is standalone • Special instructions to load and store • Assembler • Easy assembly of code • Effort to write assembler paid off • Assembled ~100 programs for testing

  4. Instruction Set • 30 instructions designed • 28 instructions implemented • Not enough time for mult or div • 2 instructions “borrow” opcodes • Needed more opcodes • Not really pseudo-instructions • Have their own datapath and control

  5. Instruction Set • Arithmetic • add, sub • Planned mult, div • Logical • and, or, xor, nand, nor, xnor, slt • andi, ori • sll, srl • Branch • beq, bne

  6. Instruction Set • Register • copy, swap, lui • swra, lwra • Memory • lw, sw, mtm • Jump • j, jr, jal, jm, jra

  7. Development • Website documenting progress • Includes all documentation • Progressive datapath construction • Used for design, implementation, testing • Groups of instructions at each step • Test cases • Ensure soundness of design • Include obscure and uncommon cases

  8. Development Problems • Xilinx state diagram and Verilog • Spent over a week attempting to fix it • Advised to use ABEL instead

  9. Datapath • 16-bit memory addresses • 16-bit data bus • 8 registers in register file • 7 static registers • PC, IR, RA, MDR, ALUOut, A, B

  10. Register Name Save Type Description 0 $zero - Value is always zero. 1 $t0 caller Temporary 2 $t1 caller Temporary 3 $t2 caller Temporary 4 $s0 callee Preserved across function calls 5 $s1 callee Preserved across function calls 6 $v caller Return value 7 $sp callee Stack pointer Register File

  11. Control

  12. Testing • 104 proposed test cases • Make sure basic instructions work first • Cannot test every value, so go for exceptions and extremes • Assembler to speed up process • Easy implementation of new programs

  13. Xilinx Implementation • Implementation on 4010XLPC84 • Did not fit on device (179% of CLBs) • 719 / 400 CLBs • 128 32x1 RAMs • 1170 4-in LUTs • 360 3-in LUTs • 128 / 880 Bounded IOBs

  14. Xilinx Implementation • Implementation on 4028XLHQ240-09 • We picked this device at random • Device usage • 827 / 1024 CLBs • 229 / 2048 CLB flip flops • 1426 / 2048 4-in LUTs • 488 / 1024 3-in LUTs • 128 / 2176 TBUFs • 34 / 193 External IOBs

  15. Implementation Speed • Minimum period of 101.497 ns • Maximum net delay of 29.230 ns • Clock speed of 9.853 MHz

  16. Demonstration

  17. Future Improvements • Implement multiplication and division • Multiple input file support for assembler • Better pseudo-instruction substitutions by assembler

  18. Questions

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