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Recitation 2 PM/0 ~ P-Machine with registers PL/0 Code Execution. COP 3402 (Summer 2014). Announcements. TA's office hours cancelled (4-5pm) Keep checking course's webpage: first project coming soon. P-machine Overview. 1. 0. 2. 0. 0. 0. code. stack. 0 6 0 0 6 1 1 0 0 6
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Recitation 2 PM/0 ~ P-Machine with registersPL/0 Code Execution COP 3402 (Summer 2014)
Announcements • TA's office hours cancelled (4-5pm) • Keep checking course's webpage: first project coming soon.
P-machine Overview 1 0 2 0 0 0 code stack 0 6 0 0 6 1 1 0 0 6 2 4 0 0 4 3 3 0 0 4 4 1 1 0 0 5 22 0 0 1 6 8 0 0 17 7 3 0 0 4 8 14 0 0 0 9 4 0 0 5 10 3 0 0 4 11 1 1 0 1 12 13 0 0 1 13 4 0 0 4 14 3 0 0 5 15 9 0 0 1 16 7 0 0 3 17 3 0 0 4 18 9 0 0 1 19 3 0 0 5 20 9 0 0 1 21 2 0 0 0 RF R0 R8 R1 R9 … R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR PC BP SP 0 1 0 CPU
P-machine ISA • 01 – LIT R, 0, MRF[R] M; • 02 – RTN 0, 0, 0 sp bp - 1; • bp stack[sp + 3]; • pc stack[sp + 4]; • 03 – LOD R, L, M RF[R] stack[ base(L, bp) + M]; • 04 – STOR,L, M stack[ base(L, bp) + M] RF[R]; • 05 – CAL 0, L, M stack[sp + 1] 0; /* space to return value • stack[sp + 2] base(L, bp); /* static link (SL) • stack[sp + 3] bp; /* dynamic link (DL) • stack[sp + 4] pc; /* return address (RA) • bp sp + 1; • pc M; • 06 – INC 0, 0, M sp sp + M; • 07 – JMP 0, 0, M pc M; • 08 – JPC R, 0, M if RF[R] == 0 then { pc M; } • 09 – SIOR, 0, 1 print(RF[R]); • 10 – SIO R, 0, 2 read(RF[R]);
P-machine ISA • 11 – NEG i, j, k (R[i] -R[j]) • 12 - ADD i, j, k (R[i] R[j] + R[k]) • 13 - SUB i, j, k (R[i] R[j] - R[k]) • 14 - MUL i, j, k (R[i] R[j] * R[k]) • 15 - DIV i, j, k (R[i] R[j] / R[k]) • 16 - ODD i, j, k (R[i] R[i] mod 2) • 17 - MOD i, j, k (R[i] R[j] mod R[k]) • 18 - EQL i, j, k (R[i] R[j] == R[k]) • 19 - NEQ i, j, k (R[i] R[j] != R[k]) • 20 - LSS i, j, k (R[i] R[j] < R[k]) • 21 - LEQ i, j, k (R[i] R[j] <= R[k]) • 22 - GTR i, j, k (R[i] R[j] > R[k]) • 23 - GEQ i, j, k (R[i] R[j] >= R[k])
Nested Code code 0 jmp0 20 1 jmp0 15 2 jmp0 8 3 jmp0 4 4 inc 0 3 5 lod2 3 6 sto1 3 7 opr0 0 8 inc 0 4 9 lit 0 1 10 sto 0 3 11 lit 0 3 12 sto1 3 13 cal 0 4 14 opr0 0 15 inc 0 4 16 lit 0 2 17 sto 0 3 18 cal 0 8 19 opr 0 0 20 inc 0 3 21 cal 0 15 22 opr 0 0 procedure A; var y; procedure B; var x; procedure C; begin x:=y; end; begin x:=1; y:= 3; call C; end; begin y:= 2; call B; end; call A. RTN 0,0 sp bp -1; pc stack[sp + 3]; bp stack[sp + 2];
P-machine Overview Initial State 0 0 PC SP code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 R8 R1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 Initial State IR PC BP SP 0 1 0 CPU
P-machine Overview Initial State 0 0 PC SP code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 R8 R1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 Fetch… IR inc 0 0 6 PC BP SP 1 1 0 CPU
P-machine Overview 0 6 1 5 4 2 3 0 0 0 0 0 0 0 SP PC code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 R8 R1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 …Execute! IR inc 0 0 6 PC BP SP From now on, we’ll only show the result after the instruction have been executed. 1 1 6 CPU
P-machine Overview 6 5 4 3 2 1 0 0 0 0 0 0 0 0 SP PC code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 3 R8 R1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR lit 0 0 3 PC BP SP 2 1 6 CPU
Store 04 – STOR,L, M stack[ base(L, bp) + M] RF[R]; int base(l, base){ // l stand for L in the instruction format int b1; //find base L levels down b1 = base; while (l > 0) { b1 = stack[b1 + 1]; l--; } return b1; }
P-machine Overview 6 5 4 3 2 1 0 0 0 0 0 0 0 0 SP PC code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 3 R8 R1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR lit 0 0 3 PC BP SP 2 1 6 CPU
P-machine Overview 6 5 4 3 2 1 0 3 0 0 0 0 0 0 SP PC code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 3 R8 R1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR sto 0 0 4 PC BP SP 3 1 6 CPU
P-machine Overview 6 5 4 3 2 1 0 3 0 0 0 0 0 0 SP PC code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 1 R8 R1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR lit 0 0 1 PC BP SP 4 1 6 CPU
P-machine Overview 6 5 4 3 2 1 0 3 0 0 0 0 1 0 SP PC code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 1 R8 R1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR sto 0 0 5 PC BP SP 5 1 6 CPU
P-machine Overview 6 5 4 3 2 1 0 3 0 0 0 0 1 0 SP PC code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 1 R8 R1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR sto 0 0 5 Wait! Let’s break the next instruction into fetch and execute… PC BP SP 5 1 6 CPU
P-machine Overview 6 5 4 3 2 1 0 3 0 0 0 0 1 0 SP PC code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 1 R8 R1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR cal 0 0 7 FETCH PC BP SP 6 1 6 CPU
P-machine Overview 1 0 2 4 3 5 6 0 3 0 0 0 1 0 PC SP code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 1 R8 R1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR cal 0 0 7 Execute PC BP SP CAL 0, L, M stack[sp + 1] 0; stack[sp + 2] base(L, bp); stack[sp + 3] bp; stack[sp + 4] pc; bp sp + 1; pc M; 6 1 6 CPU
P-machine Overview 0 6 5 4 3 2 1 7 0 0 0 3 0 1 0 0 PC SP code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 1 R8 R1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR cal 0 0 7 Execute PC BP SP CAL 0, L, M stack[sp + 1] 0; stack[sp + 2] base(L, bp); stack[sp + 3] bp; stack[sp + 4] pc; bp sp + 1; pc M; 6 1 6 CPU
P-machine Overview 7 0 6 5 4 3 2 1 8 1 0 0 0 1 3 0 0 0 SP PC code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 1 R8 R1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR cal 0 0 7 Execute PC BP SP CAL 0, L, M stack[sp + 1] 0; stack[sp + 2] base(L, bp); stack[sp + 3] bp; stack[sp + 4] pc; bp sp + 1; pc M; 6 1 6 CPU
P-machine Overview 8 7 0 6 5 4 3 2 1 9 1 0 0 0 0 0 1 0 1 3 PC SP code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 1 R8 R1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR cal 0 0 7 Execute PC BP SP CAL 0, L, M stack[sp + 1] 0; stack[sp + 2] base(L, bp); stack[sp + 3] bp; stack[sp + 4] pc; bp sp + 1; pc M; 6 1 6 CPU
P-machine Overview 10 1 2 4 5 3 0 7 8 9 6 0 0 1 1 0 0 3 6 0 0 1 PC SP code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 1 R8 R1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR cal 0 0 7 Execute PC BP SP CAL 0, L, M stack[sp + 1] 0; stack[sp + 2] base(L, bp); stack[sp + 3] bp; stack[sp + 4] pc; bp sp + 1; pc M; 6 1 6 CPU
P-machine Overview 10 1 2 4 5 3 0 7 8 9 6 0 0 1 1 0 0 3 6 0 0 1 PC SP code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 1 R8 R1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR cal 0 0 7 Execute PC BP SP CAL 0, L, M stack[sp + 1] 0; stack[sp + 2] base(L, bp); stack[sp + 3] bp; stack[sp + 4] pc; bp sp + 1; pc M; 6 7 6 CPU
P-machine Overview 10 1 2 4 5 3 0 7 8 9 6 0 0 1 1 0 0 3 6 0 0 1 PC SP code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 1 R8 R1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR cal 0 0 7 Execute PC BP SP CAL 0, L, M stack[sp + 1] 0; stack[sp + 2] base(L, bp); stack[sp + 3] bp; stack[sp + 4] pc; bp sp + 1; pc M; 7 7 6 CPU
P-machine Overview 10 1 2 4 5 3 0 7 8 9 6 0 0 1 1 0 6 3 0 0 0 1 SP PC code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 1 R8 R1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR inc 0 0 4 PC BP SP 8 7 10 CPU
P-machine Overview 10 1 2 4 5 3 0 7 8 9 6 0 0 1 1 0 6 3 0 0 0 1 SP PC code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 3 R8 R1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR lod 0 1 4 PC BP SP 9 7 10 CPU
P-machine Overview 10 1 2 4 5 3 0 7 8 9 6 3 0 0 0 1 1 0 1 6 0 0 PC SP code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 3 R8 R1 1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR lod 1 1 5 PC BP SP 10 7 10 CPU
P-machine Overview 10 1 2 4 5 3 0 7 8 9 6 3 0 0 0 1 1 0 1 6 0 0 PC SP code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 3 R8 R1 3 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR mul 1 0 1 PC BP SP 11 7 10 CPU
P-machine Overview 10 1 2 4 5 3 0 7 8 9 6 3 0 0 0 3 1 0 1 6 0 0 PC SP code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 3 R8 R1 3 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR sto 1 1 5 PC BP SP 12 7 10 CPU
P-machine Overview 10 1 2 4 5 3 0 7 8 9 6 3 0 0 0 3 1 0 1 6 0 0 PC SP code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 3 R8 R1 1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR lit 1 0 1 PC BP SP 13 7 10 CPU
P-machine Overview 10 1 2 4 5 3 0 7 8 9 6 3 0 0 0 3 1 0 1 6 0 0 PC SP code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 2 R8 R1 1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR sub 0 0 1 PC BP SP 14 7 10 CPU
P-machine Overview 10 1 2 4 5 3 0 7 8 9 6 2 0 0 0 3 1 0 1 6 0 0 PC SP code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 2 R8 R1 1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR sto 0 1 4 PC BP SP 15 7 10 CPU
P-machine Overview 10 1 2 4 5 3 0 7 8 9 6 2 0 0 0 3 1 0 1 6 0 0 PC SP code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 1 R8 R1 1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR neq 0 0 1 PC BP SP 16 7 10 CPU
P-machine Overview 10 1 2 4 5 3 0 7 8 9 6 2 0 0 0 3 1 0 1 6 0 0 PC SP code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 1 R8 R1 1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR jpc 0 0 18 PC BP SP 17 7 10 CPU
P-machine Overview 1 2 3 4 5 6 0 14 8 9 10 11 12 13 7 7 1 0 6 1 0 0 2 0 0 18 0 3 1 0 PC SP code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 1 R8 R1 1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR cal 0 1 7 PC BP SP 7 11 10 CPU
P-machine Overview 1 2 3 4 5 6 0 14 8 9 10 11 12 13 7 7 1 0 6 1 0 0 2 0 0 18 0 3 1 0 PC SP code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 1 R8 R1 1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR inc 0 0 4 PC BP SP 8 11 14 CPU
P-machine Overview 1 2 3 4 5 6 0 14 8 9 10 11 12 13 7 7 1 0 6 1 0 0 2 0 0 18 0 3 1 0 PC SP code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 2 R8 R1 1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR lod 0 1 4 PC BP SP 9 11 14 CPU
P-machine Overview 1 2 3 4 5 6 0 14 8 9 10 11 12 13 7 7 1 0 6 1 0 0 2 0 0 18 0 3 1 0 PC SP code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 2 R8 R1 3 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR lod 1 1 5 PC BP SP 10 11 14 CPU
P-machine Overview 1 2 3 4 5 6 0 14 8 9 10 11 12 13 7 7 1 0 6 1 0 0 2 0 0 18 0 3 1 0 PC SP code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 2 R8 R1 6 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR mul 1 0 1 PC BP SP 11 11 14 CPU
P-machine Overview 1 2 3 4 5 6 0 14 8 9 10 11 12 13 7 7 1 0 6 1 0 0 2 0 0 18 0 6 1 0 PC SP code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 2 R8 R1 6 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR sto 1 1 5 PC BP SP 12 11 14 CPU
P-machine Overview 1 2 3 4 5 6 0 14 8 9 10 11 12 13 7 7 1 0 6 1 0 0 2 0 0 18 0 6 1 0 PC SP code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 2 R8 R1 1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR lit 1 0 1 PC BP SP 13 11 14 CPU
P-machine Overview 1 2 3 4 5 6 0 14 8 9 10 11 12 13 7 7 1 0 6 1 0 0 2 0 0 18 0 6 1 0 PC SP code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 1 R8 R1 1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR sub 0 0 1 PC BP SP 14 11 14 CPU
P-machine Overview 1 2 3 4 5 6 0 14 8 9 10 11 12 13 7 7 1 0 6 1 0 0 1 0 0 18 0 6 1 0 PC SP code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 1 R8 R1 1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR sto 0 1 4 PC BP SP 15 11 14 CPU
P-machine Overview 1 2 3 4 5 6 0 14 8 9 10 11 12 13 7 7 1 0 6 1 0 0 1 0 0 18 0 6 1 0 PC SP code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 0 R8 R1 1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR neq 0 0 1 PC BP SP 16 11 14 CPU
P-machine Overview 1 2 3 4 5 6 0 14 8 9 10 11 12 13 7 7 1 0 6 1 0 0 1 0 0 18 0 6 1 0 PC SP code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 0 R8 R1 1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR jpc 0 0 18 PC BP SP 18 11 14 CPU
Return 02 – RTN 0, 0, 0 sp bp - 1; bp stack[sp + 3]; pc stack[sp + 4];
P-machine Overview 02 – RTN 0, 0, 0 sp bp - 1; bp stack[sp + 3]; pc stack[sp + 4]; 10 13 12 1 11 9 2 5 3 7 14 4 6 0 8 6 7 1 0 6 1 1 0 18 0 0 0 1 0 0 SP PC Fetch code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 0 R8 R1 1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR rtn 0 0 0 PC BP SP 19 11 14 CPU
P-machine Overview 02 – RTN 0, 0, 0 sp bp - 1; bp stack[sp + 3]; pc stack[sp + 4]; 10 13 12 1 11 9 2 5 3 7 14 4 6 0 8 6 7 1 0 6 1 1 0 18 0 0 0 1 0 0 SP PC Execute code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 0 R8 R1 1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR rtn 0 0 0 PC BP SP 19 11 10 CPU
P-machine Overview 02 – RTN 0, 0, 0 sp bp - 1; bp stack[sp + 3]; pc stack[sp + 4]; 10 13 12 1 11 9 2 5 3 7 14 4 6 0 8 6 7 1 0 6 1 1 0 18 0 0 0 1 0 0 SP PC Execute code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 0 R8 R1 1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR rtn 0 0 0 PC BP SP 19 7 10 CPU
P-machine Overview 02 – RTN 0, 0, 0 sp bp - 1; bp stack[sp + 3]; pc stack[sp + 4]; 10 13 12 1 11 9 2 5 3 7 14 4 6 0 8 6 7 1 0 6 1 1 0 18 0 0 0 1 0 0 SP PC Execute code stack 0 inc 0 0 6 1 lit 0 0 3 2 sto 0 0 4 3 lit 0 0 1 4 sto 0 0 5 5 cal 0 0 7 6 jmp 0 0 19 7 inc 0 0 4 8 lod 0 1 4 9 lod 1 1 5 10 mul 1 0 1 11 sto 1 1 5 12 lit 1 0 1 13 sub 0 0 1 14 sto 0 1 4 15 neq 0 0 1 16 jpc 0 0 18 17 cal 0 1 7 18 rtn 0 0 0 19 lod 0 0 5 20 sio 0 0 1 21 rtn 0 0 0 RF R0 0 R8 R1 1 R9 R2 R10 R3 R11 R4 R12 R5 R13 R6 R14 R7 R15 IR rtn 0 0 0 PC BP SP 18 7 10 CPU